FPGA

Energy Saving Tips
1. Reduce heater's room temperature For each extra degree (Celsius) of temperature, your heater will consume 7 to 11% more energy. Adjust it to 18degrees which is also better for your health. 2. Install a programmable thermostat You will be able to control the heater's temperature during specific hours every day... 3 Jul 2010 16:46

SPI Flash configuration and data access rate
Hi, I'm implementing an FPGA prototype to do some image processing such as dead pixel correction. The xilinx FPGA will be configured with an SPI flash memory,where the .bit configuration file inside as well as dead pixel locations are stored. I want to correct the dead pixel while receiving each pixel data, comp... 5 Jul 2010 07:46

PN crashing (64 bit)
I have version 12.1 WebPack running on Vista 64. I've created a new project (the Stopwatch one in the Tutorial) and am trying to add source files. When the Add Source window appears all is OK but when I try to move to a different directory at the same level or above the one that was highlighted originally, the ... 2 Jul 2010 09:04

carrier tracking over zero frequency point
Hi All, I am developing a carrier tracking module for 16QAM receiver based on Costas loop on an fpga platform. Tracking works well on either side of zero frequency and over zero if crossing rate is several seconds or minutes apart. However it loses lock and relocks if zero crossing rate is few seconds apart. ... 3 Jul 2010 13:27

DMA operation to 64-bits PC platform
Hi, I have a custom made PCIe board with a Virtex 5 FPGA on which I implemented a DMA unit which uses the PCIe endpoint block plus v1.14. I also implemented simple read/write operations from the PC to the board (the board responds with completion TLPs). The read/write operations are working, DMA is not working ... 6 Jul 2010 06:47

Xilinx xapp175, empty + full flag really synchronous?
Hey, I found an amazing async fifo concept on the xilinx homepage. It looks that the latency to share data between clock domains is reduced to one cycle. But I'm asking if the setup + hold times are always met. I admit that setting the empty flag is correct but what about releasing, which is caused by write clo... 2 Jul 2010 14:37

Automatic BUFG insertion on a non clock signal in ISE 12.1
Hi, I have a very simple design using a latch. I know latches should not be used but it is a necessary evil in this case for speed reason. If someone can find as fast of a way to do this with synchronous logic, I would love to hear it. My question is that ISE 12.1 is inserting a BUFG in between the input ms3_n... 30 Jun 2010 20:54

Testbench
I am not sure if such a program exists, but I would like to be able to test a fairly large design by not having to write lots of testbenches. Idealy I would like a program were I could connect my DUT and give some constraints and then test vectors would be produced to test all cases within the constraints. Has anyone h... 30 Jun 2010 11:58

ML605 Dev Board Problems
We are struggling to get the ML605 board running on our Dell PowerEdge SC430 in slot 4 (x8 slot). Out of the box the unit did not recognize the card but I could view the system PCI architecture using PCITree. After building a PCIe x8 gen 1 core using ISE 12.1 (with the patch per AR#35422) per xtp0044.pdf, the unit no... 30 Jun 2010 01:04

Require a solution - LVDS support +RJ45 connectors
On Jun 29, 2:38 pm, "sharath20284" <sharath20284(a)n_o_s_p_a_m.yahoo.com> wrote: Hello, I am not sure if this post is in the right place - I hope to get some help I am looking for a PCI/e based FPGA solution - The board should be able to support LVDS with 2 RJ45 i/o ports which connect to CAT5 cables. ... 30 Jun 2010 09:44