FPGA
in [Hardware]
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LXT972 pass-through packet Hello. I have designed an ethernet interface with a Xilinx Virtex 5 FPGA and a LXT972 Intel's IC. Besides, I have a GUI designed in the computer host to send/receive files and information. Using a sniffer, I can see sometimes that data coming back from the board is read as pass-through packets, instead of having th... 7 Jul 2010 06:51
EEBlaster - USB-JTAG-tool for Altera HOT SUMMER OFFER To all the Altera users here: If you order at least 3 EEBlasters (EUR49,-/pcs), you will get free shipping inside Europe, when you mention "HOT SUMMER" in the remarks-field of the order form. The EEBlaster can be ordered at: http://www.entner-electronics.com/tl/index.php/eeblaster.html The ... 7 Jul 2010 04:41
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6 kbytes BRAM and Xst:2260 I'm using Coregen on XC2S200 to generate a 6144 bytes (12 blocks) BRAM and I get these infos: INFO:Xst:2260 - The FF/Latch <BU16> in Unit <test> is equivalent to the following 3 FFs/Latches : <BU97> <BU178> <BU259> INFO:Xst:2260 - The FF/Latch <BU19> in Unit <test> is equivalent to the following 3 FFs/Latches ... 6 Jul 2010 23:19
spartan 3xc3s4000 daisy chain help required Hi, I am using spartan 3 FPGAs and 1 EEPROM XCF16P in daisy chain configuration and programming it through JTAG but i am getting this error continuously " DONE did not go high".The TDI of JTAG is connected to TDI of EEPROM, TDO of EEPROM is connected to TDI of FPGA1 and so on. I have double checked the hardware but... 7 Jul 2010 01:29
FPGA Video processing board (HDMI).. who makes one? Does anyone make the following: HDMI Receiver -> FPGA -> HDMI Transmitter I would considder DVI/Displayport also. I just want this for video processing. I don't need audio, controls, PCIe, etc. I've seen some very large boards with HDMI daughter boards but they're way too large and unnecessary for just testin... 8 Jul 2010 14:42
Q: Standard Programming Idiom Hi all, I just came across a - what I think - must be a quite standard programming idiom for implementing an FSM. Essentially, I read a byte value byte_in sequentially, and assign it to the appropriate portions of signal register. As you can see, the read_en signal must be HIGH in the state before the data in b... 6 Jul 2010 03:32
Difference between DDR and DDR2 I'm trying to see the difference from an external point of view, and I can't see one, apart from having a 1.8V supply rather than a 2.5V. I can see increased clock speed and increased clock latency, but that's about it I am aware the internal clock runs at half main clock, and that the burst order in interleav... 6 Jul 2010 06:47
software for xc3000 I'm looking for Xilinx Foundation 3.1i or XACT 5 or 6 because I want to use XC3000 FPGA. I know, that chips are very old but I don't want scrap it. Maybe someone has copy? Thanks Krzych ... 5 Jul 2010 15:31
xilinx leadtimes Avnet is sole disti for Xilinx, now lets see what Avnet says: searching for Spartan-6 all items are no stock, with notice factory leadtime 16 weeks but some items have extra note, "stock in asia" good this means there is stock? but what does the "stock in asia" link do? it opens a popup window saying: no stoc... 8 Jul 2010 03:42 |