FPGA

Embedded Multipliers in Altera Cyclone
Hi all, In my Cyclone 4 based design I'm getting an embedded multiplier inferred, as expected from the following VHDL: C <= A * B; (where A and B are registered 12 bit values, and the output C is subsequently registered, with no other logic in the path) However I'm seeing a timing violation on this path. ... 28 Jul 2010 05:16

Performing incremental code coverage with modelsim
Hello, I would like to run several simulations one after another with code coverage on modelsim. This is because I have several testbenches, each one testing a particular aspect of the design. However I would like, at the end, to get a coverage report taking in account every simulations I have run. I believe t... 26 Jul 2010 12:43

temporal logic folding
all, I would like some feedback on a new FPGA architecture. Are there any serious configurable logic gurus on this group? If there is interest, I will post links to the 3 published papers that discuss in detail a logic architecture that offers better than 10x higher logic density than standard FPGA, along with... 27 Jul 2010 17:15

Connecting "signed" to "std_logic_vector" ports.
Hi, As I understand it, good practice dictates that in a synthesis-targeted setting, components should use ports of type std_logic or std_logic_vector only. Certainly Xilinx's IP generation tools provide components with this philosophy. My design is well-suited to the use of signed types from IEEE.Numeri... 5 Aug 2010 11:18

sdram stable clock
1.What is a stable clock? 2.How can i generate using DCM in xilinx? or vhdl? --------------------------------------- Posted through http://www.FPGARelated.com ... 26 Jul 2010 18:15

FPGA < -- > Processor timing Violations
Hi, I'm interfacing Actel FPGA with Freescale Coldfire Processor. This interface is operating @ 75Mhz. FPGA output signal (TA -Transfer acknowledge) and FPGA data out is sampled at rising edge by Processor. As per Coldfire Processor datasheet, setup time for this signals is 9ns and 0ns is hold time. I am g... 26 Jul 2010 06:11

Programming the Actel Smartfusion Eval Kit in Linux
Hello, I'm also a linux user for most of my work. On the other hand, Windows is not that bad or expensive so I just dual boot. Actel is doing a great job for a smaller company by releasing their mainline development code as a linux version but some of the outlier tools, like FlashPro, are still Windows only as ... 25 Jul 2010 23:47

Altera EDA Netlist Writer
Hi, Using Altera Model-Sim to do a gate level simulation. The .vo file that is produced doesn't seem to be modeling the internal RAM's correctly. In the design they are instantiated as 12bit but the EDA netlist has them as 4 bits. Any help on this? Has anyone experienced a similar problem? Regards, Rob ... 26 Jul 2010 05:07

Weighted Round Robin Arbiter
Hi everyone, Can someone kindly provide any good links/tutorials/articles for implementing weighted round robin (WRR) arbitration? Thank you. --------------------------------------- Posted through http://www.FPGARelated.com ... 24 Jul 2010 23:05

Is Tier Logic doomed ? :-/
"another one bytes the dust"... According to Processor Watch - July 22, 2010 (sorry, I have no URL, it was sent to me by email) ================================================ Tears for Tier Logic By Tom R. Halfhill, Senior Editor, MPR (7/19/2010) FPGA startup Tier Logic looks doomed after failing to raise... 24 Jul 2010 09:04