24Hz to 60Hz PLL?
in [Design]
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From: Vladimir Vassilevsky on 12 Feb 2010 18:29 Jim Thompson wrote: > On Fri, 12 Feb 2010 17:31:20 -0500, Spehro Pefhany > <speffSNIP(a)interlogDOTyou.knowwhat> wrote: > > >>On Fri, 12 Feb 2010 14:14:04 -0800 (PST), Chris >><christopher.maness(a)gmail.com> wrote: >> >> >>>I need to make a PLL that slaves to a 24Hz square wave. The output of >>>the loop would be a 60Hz square wave. Any CMOS level chips that would >>>be good for this? I understand that I would need to divide by a >>>decimal value of 2.5 for the loop. >>> >>>Thanks, >>>Chris Maness >> >>You could phase lock the 24Hz (movie frame rate?) to a 120Hz VCO >>divided by 5, and divide the 120Hz by 2 to get 60Hz. > > > Low frequency PLL's often present competing needs for fast lock and > low jitter. Just another reason for doing it in the software. You can achieve an approximate lock just in one period and then fine tune it as accurate and low jittery as you need. > So I've always been fond of this approach which "jerk" > locks an "oscillator" created with a shift-register and a stable clock > (dating back to 1983, where I had to extract data from a floppy whose > orientation and physical acceleration were PITA).... > > http://analog-innovations.com/SED/FloppyDataExtractor.pdf I have to synchronize different clocks to GPS 1Hz output to the accuracy of 1e-9 or so... Vladimir Vassilevsky DSP and Mixed Signal Design Consultant http://www.abvolt.com
From: Tim Wescott on 12 Feb 2010 18:35 On Fri, 12 Feb 2010 15:07:33 -0800, Chris wrote: > On Feb 12, 2:47 pm, Chris <christopher.man...(a)gmail.com> wrote: >> On Feb 12, 2:31 pm, Spehro Pefhany <speffS...(a)interlogDOTyou.knowwhat> >> wrote: >> >> > On Fri, 12 Feb 2010 14:14:04 -0800 (PST), Chris >> >> > <christopher.man...(a)gmail.com> wrote: >> > >I need to make a PLL that slaves to a 24Hz square wave. The output >> > >of the loop would be a 60Hz square wave. Any CMOS level chips that >> > >would be good for this? I understand that I would need to divide by >> > >a decimal value of 2.5 for the loop. >> >> > >Thanks, >> > >Chris Maness >> >> > You could phase lock the 24Hz (movie frame rate?) to a 120Hz VCO >> > divided by 5, and divide the 120Hz by 2 to get 60Hz. >> >> That sounds better than trying to find a divide by 2.5. What chips >> would suggest to accomplish the divide by 5? Are there complete PLL >> chips that can be programed to divide by an odd number? >> >> Yes, it is a 1 pulse/frame to pilot tone converter. Similar to: >> >> http://www.webtfg.com/sync11.htm >> >> However, this is not primarily intended to have a record level sine >> wave out like "The Film Group" unit. I need a full 12V swing as an >> input to a perforated tape deck for the sync motor in the unit. Ideally >> I could have a lower level output to a digital recorder. This could in >> turn be amplified upon playback and fed back to the perforated tape >> deck. This would "resolve" the speed variations from the camera. When >> the film is played back referenced to a crystal, it would be synced to >> the film once the film has been scanned in to a frame accurate >> telecine. >> >> Thanks, >> Chris Maness > > Here is what I have so far: > > Looking at the CD4046b data sheet, it looks like the most straight > forward design would be a Camera --> NE555 (to lengthen the 5ms pulse > from the camera to 21ms for real square wave. I am not sure if this > would be needed by the comparator)--> CD4046 (With an Divide by N CD4059 > dividing by 5)-->CD4060 ( Signal Out from Q2 would be divide by 2). > > I already have a bunch of CD4060's from my last project. I also have > some NE556's. Seems very easy. > > Thanks, > Chris Maness Yup, except that you don't need the 555 if you're using a digital in -- for that you want to use the 3-state phase/frequency comparator in the 4046, which is edge sensitive anyway. -- www.wescottdesign.com
From: Martin Riddle on 12 Feb 2010 19:01 "Vladimir Vassilevsky" <nospam(a)nowhere.com> wrote in message news:UqOdnWHSjYZDQOjWnZ2dnUVZ_gGdnZ2d(a)giganews.com... > > > Chris wrote: > >> I need to make a PLL that slaves to a 24Hz square wave. The output >> of >> the loop would be a 60Hz square wave. Any CMOS level chips that >> would >> be good for this? I understand that I would need to divide by a >> decimal value of 2.5 for the loop. > > Use a PIC. > > Lock on 24 Hz by input capture, generate 60 Hz by output compare. Do > all PLL logic in software. There will be a jitter of +/-1 timer clock, > however this will be much better then suggested analog solutions. > > > Vladimir Vassilevsky > DSP and Mixed Signal Design Consultant > http://www.abvolt.com Hi Vladimir, Is there good reading references for doing a software PLL anywhere. So far in my casual searches, I've found very little on a software implementation. Cheers
From: Spehro Pefhany on 12 Feb 2010 19:34 On Fri, 12 Feb 2010 15:07:33 -0800 (PST), the renowned Chris <christopher.maness(a)gmail.com> wrote: >On Feb 12, 2:47�pm, Chris <christopher.man...(a)gmail.com> wrote: >> On Feb 12, 2:31�pm, Spehro Pefhany <speffS...(a)interlogDOTyou.knowwhat> >> wrote: >> >> > On Fri, 12 Feb 2010 14:14:04 -0800 (PST), Chris >> >> > <christopher.man...(a)gmail.com> wrote: >> > >I need to make a PLL that slaves to a 24Hz square wave. �The output of >> > >the loop would be a 60Hz square wave. �Any CMOS level chips that would >> > >be good for this? �I understand that I would need to divide by a >> > >decimal value of 2.5 for the loop. >> >> > >Thanks, >> > >Chris Maness >> >> > You could phase lock the 24Hz (movie frame rate?) to a 120Hz VCO >> > divided by 5, and divide the 120Hz by 2 to get 60Hz. >> >> That sounds better than trying to find a divide by 2.5. �What chips >> would suggest to accomplish the divide by 5? �Are there complete PLL >> chips that can be programed to divide by an odd number? >> >> Yes, it is a 1 pulse/frame to pilot tone converter. �Similar to: >> >> http://www.webtfg.com/sync11.htm >> >> However, this is not primarily intended to have a record level sine >> wave out like "The Film Group" unit. �I need a full 12V swing as an >> input to a perforated tape deck for the sync motor in the unit. >> Ideally I could have a lower level output to a digital recorder. �This >> could in turn be amplified upon playback and fed back to the >> perforated tape deck. �This would "resolve" the speed variations from >> the camera. �When the film is played back referenced to a crystal, it >> would be synced to the film once the film has been scanned in to a >> frame accurate telecine. >> >> Thanks, >> Chris Maness > >Here is what I have so far: > >Looking at the CD4046b data sheet, it looks like the most straight >forward design would be a Camera --> NE555 (to lengthen the 5ms pulse >from the camera to 21ms for real square wave. I am not sure if this >would be needed by the comparator)--> CD4046 (With an Divide by N >CD4059 dividing by 5)-->CD4060 ( Signal Out from Q2 would be divide by >2). As JL suggested, the 74HC390 (modern dual version of the old 7490 with power pins in the normal positions) will give you both divide by 2 and 5, with half a chip left over. >I already have a bunch of CD4060's from my last project. I also have >some NE556's. Seems very easy. > >Thanks, >Chris Maness Best regards, Spehro Pefhany -- "it's the network..." "The Journey is the reward" speff(a)interlog.com Info for manufacturers: http://www.trexon.com Embedded software/hardware/analog Info for designers: http://www.speff.com
From: Tim Wescott on 12 Feb 2010 19:42
On Fri, 12 Feb 2010 19:01:46 -0500, Martin Riddle wrote: > "Vladimir Vassilevsky" <nospam(a)nowhere.com> wrote in message > news:UqOdnWHSjYZDQOjWnZ2dnUVZ_gGdnZ2d(a)giganews.com... >> >> >> Chris wrote: >> >>> I need to make a PLL that slaves to a 24Hz square wave. The output of >>> the loop would be a 60Hz square wave. Any CMOS level chips that would >>> be good for this? I understand that I would need to divide by a >>> decimal value of 2.5 for the loop. >> >> Use a PIC. >> >> Lock on 24 Hz by input capture, generate 60 Hz by output compare. Do >> all PLL logic in software. There will be a jitter of +/-1 timer clock, >> however this will be much better then suggested analog solutions. >> >> >> Vladimir Vassilevsky >> DSP and Mixed Signal Design Consultant http://www.abvolt.com > > Hi Vladimir, Is there good reading references for doing a software PLL > anywhere. > So far in my casual searches, I've found very little on a software > implementation. No, but here you go. This will be a complete document, with introduction, discussion, analysis, and a conclusion: Making digital PLLs in software is fun and easy (introduction). They're just like hardware PLL's (discussion) except where they're different (analysis). But they're easy, if you think hard. So go do it! (conclusion). Was that too terse? -- www.wescottdesign.com |