24Hz to 60Hz PLL?
in [Design]
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From: John Larkin on 13 Feb 2010 17:16 On Sat, 13 Feb 2010 12:53:07 -0800 (PST), whit3rd <whit3rd(a)gmail.com> wrote: >On Feb 12, 2:44�pm, John Larkin ><jjlar...(a)highNOTlandTHIStechnologyPART.com> wrote: >> On Fri, 12 Feb 2010 14:14:04 -0800 (PST), Chris >> >> <christopher.man...(a)gmail.com> wrote: >> >I need to make a PLL that slaves to a 24Hz square wave. �The output of >> >the loop would be a 60Hz square wave. > >> CD or HC 4046, with a slow loop. Divide 24 by 2 and divide 60 by five >> and lock at 12 Hz. > >Right chip, but the best strategy is to lock a high frequency to a >multiple >of the 24 Hz, NOT to lock at 12 Hz. The loop filter works better at >the highest frequency, and the noise pickup would improve if >you went higher than that. Then, divide 240 by 4 to get the 60 Hz, >and by five then by two to get the 24 Hz for the phase comparison. > >The 'divide by two' on each branch guarantees accurate 50% duty cycle, >many >counters have asymmetric outputs. The input only furnishes information 24 times a second (48 if you can use both edges) so it doesn't much matter what the oscillator frequency is. The VCO could be 60KHz and the loop dynamics wouldn't be any better. Granted, 24 is twice as good as 12. So you could run the VCO at 120, and then divide by 5 to get 24 for the pll, and also divide by 2 to get the 60. The phase:frequency detector in the 4046 is edge sensitive, so duty cycle doesn't matter if you use that one. John
From: Jim Thompson on 13 Feb 2010 17:39 On Sat, 13 Feb 2010 14:16:57 -0800, John Larkin <jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: >On Sat, 13 Feb 2010 12:53:07 -0800 (PST), whit3rd <whit3rd(a)gmail.com> >wrote: > >>On Feb 12, 2:44�pm, John Larkin >><jjlar...(a)highNOTlandTHIStechnologyPART.com> wrote: >>> On Fri, 12 Feb 2010 14:14:04 -0800 (PST), Chris >>> >>> <christopher.man...(a)gmail.com> wrote: >>> >I need to make a PLL that slaves to a 24Hz square wave. �The output of >>> >the loop would be a 60Hz square wave. >> >>> CD or HC 4046, with a slow loop. Divide 24 by 2 and divide 60 by five >>> and lock at 12 Hz. >> >>Right chip, but the best strategy is to lock a high frequency to a >>multiple >>of the 24 Hz, NOT to lock at 12 Hz. The loop filter works better at >>the highest frequency, and the noise pickup would improve if >>you went higher than that. Then, divide 240 by 4 to get the 60 Hz, >>and by five then by two to get the 24 Hz for the phase comparison. >> >>The 'divide by two' on each branch guarantees accurate 50% duty cycle, >>many >>counters have asymmetric outputs. > >The input only furnishes information 24 times a second (48 if you can >use both edges) so it doesn't much matter what the oscillator >frequency is. The VCO could be 60KHz and the loop dynamics wouldn't be >any better. > >Granted, 24 is twice as good as 12. So you could run the VCO at 120, >and then divide by 5 to get 24 for the pll, and also divide by 2 to >get the 60. > >The phase:frequency detector in the 4046 is edge sensitive, so duty >cycle doesn't matter if you use that one. > >John John's last paragraph is absolutely correct... Ron Treadway and I designed it to be that way :-P ...Jim Thompson -- | James E.Thompson, CTO | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona 85048 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.
From: BobW on 13 Feb 2010 17:54 "Jim Thompson" <To-Email-Use-The-Envelope-Icon(a)My-Web-Site.com> wrote in message news:ofaen5hs1erom244nbvj7ajqd87vt22of3(a)4ax.com... > On Sat, 13 Feb 2010 14:16:57 -0800, John Larkin > <jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: > >>On Sat, 13 Feb 2010 12:53:07 -0800 (PST), whit3rd <whit3rd(a)gmail.com> >>wrote: >> >>>On Feb 12, 2:44 pm, John Larkin >>><jjlar...(a)highNOTlandTHIStechnologyPART.com> wrote: >>>> On Fri, 12 Feb 2010 14:14:04 -0800 (PST), Chris >>>> >>>> <christopher.man...(a)gmail.com> wrote: >>>> >I need to make a PLL that slaves to a 24Hz square wave. The output of >>>> >the loop would be a 60Hz square wave. >>> >>>> CD or HC 4046, with a slow loop. Divide 24 by 2 and divide 60 by five >>>> and lock at 12 Hz. >>> >>>Right chip, but the best strategy is to lock a high frequency to a >>>multiple >>>of the 24 Hz, NOT to lock at 12 Hz. The loop filter works better at >>>the highest frequency, and the noise pickup would improve if >>>you went higher than that. Then, divide 240 by 4 to get the 60 Hz, >>>and by five then by two to get the 24 Hz for the phase comparison. >>> >>>The 'divide by two' on each branch guarantees accurate 50% duty cycle, >>>many >>>counters have asymmetric outputs. >> >>The input only furnishes information 24 times a second (48 if you can >>use both edges) so it doesn't much matter what the oscillator >>frequency is. The VCO could be 60KHz and the loop dynamics wouldn't be >>any better. >> >>Granted, 24 is twice as good as 12. So you could run the VCO at 120, >>and then divide by 5 to get 24 for the pll, and also divide by 2 to >>get the 60. >> >>The phase:frequency detector in the 4046 is edge sensitive, so duty >>cycle doesn't matter if you use that one. >> >>John > > John's last paragraph is absolutely correct... Ron Treadway and I > designed it to be that way :-P > > ...Jim Thompson Really? I loved the 4046 and used it in several designs. Bob -- == All google group posts are automatically deleted due to spam ==
From: Phil Hobbs on 13 Feb 2010 20:36 On 2/13/2010 5:39 PM, Jim Thompson wrote: > On Sat, 13 Feb 2010 14:16:57 -0800, John Larkin > <jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: > >> On Sat, 13 Feb 2010 12:53:07 -0800 (PST), whit3rd<whit3rd(a)gmail.com> >> wrote: >> >>> On Feb 12, 2:44 pm, John Larkin >>> <jjlar...(a)highNOTlandTHIStechnologyPART.com> wrote: >>>> On Fri, 12 Feb 2010 14:14:04 -0800 (PST), Chris >>>> >>>> <christopher.man...(a)gmail.com> wrote: >>>>> I need to make a PLL that slaves to a 24Hz square wave. The output of >>>>> the loop would be a 60Hz square wave. >>> >>>> CD or HC 4046, with a slow loop. Divide 24 by 2 and divide 60 by five >>>> and lock at 12 Hz. >>> >>> Right chip, but the best strategy is to lock a high frequency to a >>> multiple >>> of the 24 Hz, NOT to lock at 12 Hz. The loop filter works better at >>> the highest frequency, and the noise pickup would improve if >>> you went higher than that. Then, divide 240 by 4 to get the 60 Hz, >>> and by five then by two to get the 24 Hz for the phase comparison. >>> >>> The 'divide by two' on each branch guarantees accurate 50% duty cycle, >>> many >>> counters have asymmetric outputs. >> >> The input only furnishes information 24 times a second (48 if you can >> use both edges) so it doesn't much matter what the oscillator >> frequency is. The VCO could be 60KHz and the loop dynamics wouldn't be >> any better. >> >> Granted, 24 is twice as good as 12. So you could run the VCO at 120, >> and then divide by 5 to get 24 for the pll, and also divide by 2 to >> get the 60. >> >> The phase:frequency detector in the 4046 is edge sensitive, so duty >> cycle doesn't matter if you use that one. >> >> John > > John's last paragraph is absolutely correct... Ron Treadway and I > designed it to be that way :-P > > ...Jim Thompson So how come you put that stupid deadband in there? ;) Cheers Phil Hobbs -- Dr Philip C D Hobbs Principal ElectroOptical Innovations 55 Orchard Rd Briarcliff Manor NY 10510 845-480-2058 hobbs at electrooptical dot net http://electrooptical.net
From: Jim Thompson on 13 Feb 2010 21:08
On Sat, 13 Feb 2010 20:36:35 -0500, Phil Hobbs <pcdhSpamMeSenseless(a)electrooptical.net> wrote: >On 2/13/2010 5:39 PM, Jim Thompson wrote: >> On Sat, 13 Feb 2010 14:16:57 -0800, John Larkin >> <jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: >> >>> On Sat, 13 Feb 2010 12:53:07 -0800 (PST), whit3rd<whit3rd(a)gmail.com> >>> wrote: >>> >>>> On Feb 12, 2:44 pm, John Larkin >>>> <jjlar...(a)highNOTlandTHIStechnologyPART.com> wrote: >>>>> On Fri, 12 Feb 2010 14:14:04 -0800 (PST), Chris >>>>> >>>>> <christopher.man...(a)gmail.com> wrote: >>>>>> I need to make a PLL that slaves to a 24Hz square wave. The output of >>>>>> the loop would be a 60Hz square wave. >>>> >>>>> CD or HC 4046, with a slow loop. Divide 24 by 2 and divide 60 by five >>>>> and lock at 12 Hz. >>>> >>>> Right chip, but the best strategy is to lock a high frequency to a >>>> multiple >>>> of the 24 Hz, NOT to lock at 12 Hz. The loop filter works better at >>>> the highest frequency, and the noise pickup would improve if >>>> you went higher than that. Then, divide 240 by 4 to get the 60 Hz, >>>> and by five then by two to get the 24 Hz for the phase comparison. >>>> >>>> The 'divide by two' on each branch guarantees accurate 50% duty cycle, >>>> many >>>> counters have asymmetric outputs. >>> >>> The input only furnishes information 24 times a second (48 if you can >>> use both edges) so it doesn't much matter what the oscillator >>> frequency is. The VCO could be 60KHz and the loop dynamics wouldn't be >>> any better. >>> >>> Granted, 24 is twice as good as 12. So you could run the VCO at 120, >>> and then divide by 5 to get 24 for the pll, and also divide by 2 to >>> get the 60. >>> >>> The phase:frequency detector in the 4046 is edge sensitive, so duty >>> cycle doesn't matter if you use that one. >>> >>> John >> >> John's last paragraph is absolutely correct... Ron Treadway and I >> designed it to be that way :-P >> >> ...Jim Thompson > >So how come you put that stupid deadband in there? ;) > >Cheers > >Phil Hobbs That's a mismatched delay issue. Later versions have that "fixed" by overlapping the U/D outputs. ...Jim Thompson -- | James E.Thompson, CTO | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona 85048 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food. |