24Hz to 60Hz PLL?
in [Design]
|
From: Michael A. Terrell on 14 Feb 2010 14:15 Vladimir Vassilevsky wrote: > > Just another reason for doing it in the software. You can achieve an > approximate lock just in one period and then fine tune it as accurate > and low jittery as you need. Only if you don't know how to do it without a microprocessor. PLLs were around long before using your method. The ones we built for deep space telemetry had TTL inputs for the dividers, but they could be programmed with anything from a diode array to thumb wheel switches long before a microprocessor was cheap enough. We achieved a very low phase noise in the output without using your method, with extremely low reference frequency leak through. The settling time was quite good, as well. the same methods worked well at lower frequencies, as well. Since he only wants one ratio, there is no need to go to your extreme overkill. -- Greed is the root of all eBay.
From: Jim Thompson on 14 Feb 2010 14:49 On Sun, 14 Feb 2010 14:15:42 -0500, "Michael A. Terrell" <mike.terrell(a)earthlink.net> wrote: > >Vladimir Vassilevsky wrote: >> >> Just another reason for doing it in the software. You can achieve an >> approximate lock just in one period and then fine tune it as accurate >> and low jittery as you need. > > > Only if you don't know how to do it without a microprocessor. PLLs >were around long before using your method. The ones we built for deep >space telemetry had TTL inputs for the dividers, but they could be >programmed with anything from a diode array to thumb wheel switches long >before a microprocessor was cheap enough. > > We achieved a very low phase noise in the output without using your >method, with extremely low reference frequency leak through. The >settling time was quite good, as well. the same methods worked well at >lower frequencies, as well. Since he only wants one ratio, there is no >need to go to your extreme overkill. When I demonstrated (~1968) my first analog PLL (for aircraft ADF) pulling out a signal completely buried in noise, none other than Gardner himself said it couldn't be working :-) For the OP, since he has a "square" source of 24Hz, I'd simply use a PFD, a VCO at ~120Hz, DIV5 as feedback, DIV2 from VCO to get 60Hz. ...Jim Thompson -- | James E.Thompson, CTO | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona 85048 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.
From: Jim Thompson on 14 Feb 2010 15:15 On Sun, 14 Feb 2010 12:49:03 -0700, Jim Thompson <To-Email-Use-The-Envelope-Icon(a)My-Web-Site.com> wrote: >On Sun, 14 Feb 2010 14:15:42 -0500, "Michael A. Terrell" ><mike.terrell(a)earthlink.net> wrote: > >> >>Vladimir Vassilevsky wrote: >>> >>> Just another reason for doing it in the software. You can achieve an >>> approximate lock just in one period and then fine tune it as accurate >>> and low jittery as you need. >> >> >> Only if you don't know how to do it without a microprocessor. PLLs >>were around long before using your method. The ones we built for deep >>space telemetry had TTL inputs for the dividers, but they could be >>programmed with anything from a diode array to thumb wheel switches long >>before a microprocessor was cheap enough. >> >> We achieved a very low phase noise in the output without using your >>method, with extremely low reference frequency leak through. The >>settling time was quite good, as well. the same methods worked well at >>lower frequencies, as well. Since he only wants one ratio, there is no >>need to go to your extreme overkill. > >When I demonstrated (~1968) my first analog PLL (for aircraft ADF) >pulling out a signal completely buried in noise, none other than >Gardner himself said it couldn't be working :-) > >For the OP, since he has a "square" source of 24Hz, I'd simply use a >PFD, a VCO at ~120Hz, DIV5 as feedback, DIV2 from VCO to get 60Hz. > > ...Jim Thompson Elaborating: Those suggesting harmonic filtering... 3rd Harmonic of 24Hz is 72Hz 5th Harmonic of 24Hz is 120Hz Not an easy filtering job to keep the 3rd from "wobbulating" everything ;-) ...Jim Thompson -- | James E.Thompson, CTO | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona 85048 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.
From: Tim Wescott on 14 Feb 2010 17:08 On Sun, 14 Feb 2010 12:49:03 -0700, Jim Thompson wrote: > On Sun, 14 Feb 2010 14:15:42 -0500, "Michael A. Terrell" > <mike.terrell(a)earthlink.net> wrote: > > >>Vladimir Vassilevsky wrote: >>> >>> Just another reason for doing it in the software. You can achieve an >>> approximate lock just in one period and then fine tune it as accurate >>> and low jittery as you need. >> >> >> Only if you don't know how to do it without a microprocessor. PLLs >>were around long before using your method. The ones we built for deep >>space telemetry had TTL inputs for the dividers, but they could be >>programmed with anything from a diode array to thumb wheel switches long >>before a microprocessor was cheap enough. >> >> We achieved a very low phase noise in the output without using your >>method, with extremely low reference frequency leak through. The >>settling time was quite good, as well. the same methods worked well at >>lower frequencies, as well. Since he only wants one ratio, there is no >>need to go to your extreme overkill. > > When I demonstrated (~1968) my first analog PLL (for aircraft ADF) > pulling out a signal completely buried in noise, none other than Gardner > himself said it couldn't be working :-) > > For the OP, since he has a "square" source of 24Hz, I'd simply use a > PFD, a VCO at ~120Hz, DIV5 as feedback, DIV2 from VCO to get 60Hz. > > ...Jim Thompson These days the least PCB space way to do this may well be with a digital PLL in a microprocessor -- if this is _all_ you're doing you can do it with _just_ a PIC in an SO-8 or smaller package; doing this in analog without a dedicated chip will take at least two 14- or 16-pin chips (4046 and a 74xx counter), plus a small handful of resistors and some not-too- small caps. But one wants to choose something that is known to work, and fits with the OP's abilities and situation. In a product I'd probably do it with a micro; for a one-off I'd probably do it the 'analog' way. -- www.wescottdesign.com
From: Chris on 14 Feb 2010 19:12
On Feb 14, 8:10 am, MooseFET <kensm...(a)rahul.net> wrote: > On Feb 13, 12:31 pm, Chris <christopher.man...(a)gmail.com> wrote: > > > > > On Feb 13, 10:14 am, MooseFET <kensm...(a)rahul.net> wrote: > > > > On Feb 13, 8:20 am, Vladimir Vassilevsky <nos...(a)nowhere.com> wrote: > > > > > MooseFET wrote: > > > > > On Feb 12, 3:01 pm, Vladimir Vassilevsky <nos...(a)nowhere.com> wrote: > > > > > >>Chris wrote: > > > > > >>>I need to make a PLL that slaves to a 24Hz square wave. The output of > > > > >>>the loop would be a 60Hz square wave. Any CMOS level chips that would > > > > >>>be good for this? I understand that I would need to divide by a > > > > >>>decimal value of 2.5 for the loop. > > > > > >>Use a PIC. > > > > > > No, the 8051 is the right processor for this. > > > > > Personally I despise PICs. However PIC became a generic word for any > > > > small microcontroller. Once a customer asked me if I work with PIC > > > > controllers made by AVR company. > > > > The PIC isn't all that bad. It is just a little weirder than it > > > needed > > > to be. I think part of it is because they did'nt think through the > > > step > > > to the next larger size. > > > > When they designed the assembler for it, they compounded the > > > weirdness. > > > Given what it can do, a assembler that took expressions like: > > > > A += Variable > > > Variable += A > > > > would have made it easier to read. > > > > > Vladimir Vassilevsky > > > > DSP and Mixed Signal Design Consultanthttp://www.abvolt.com > > > Well the reason I am straying away from the MCU idea is that I really > > want to just finish the project. I am doing it in my spare time. If > > I could program it in about the same amount of time it would take me > > to put together the aforementioned list of parts, then I am all ears. > > However, never having messed around with programing a chip before, I > > am thinking this could take another couple of dozen hours to > > accomplish the task (factoring in a learning curve). > > > However, if you guys think that the signal from my design would be too > > jittery to be useful than I guess I don't have a choice, but to take > > the MCU route. > > Since you only need to work over a very narrow range, you can use a > crystal > in the VCO part of the PLL. If you hunt among the frequencies you can > get > from digikey, I think you will easily find one that you can pull onto > a > power of two times 60Hz. A very simple flip-flop based phase detector > can > get a low jitter correction signal. A slightly more complex on based > on some > tristating can get you even lower. > > Enable the circuit output just before the "expected" rise of the 24Hz > Follow the 24Hz input until after the "expected" rise. > > The "expected" value is a small number of clock cycles of the crystal. > This can either be picked by the designer or learned by the circuit > by decrementing the width until it just brackets the rise or > incrementing > if the rise goes outside the expected band. > > This method has the noise rejection characteristics of the XOR method > for the case where there is a small noise in the input. It doesn't > have > a gain change as you go through the perfectly aligned case. This > means > that you can use a more extreme filter than the flip-flop case > normally > allows. > > This PLL will be following a movie camera that can vary in speed a few percent. I doubt that I would be able to push or pull and xtal that far off of it's designed freq. Chris |