24Hz to 60Hz PLL?
in [Design]
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From: Martin Riddle on 12 Feb 2010 21:11 "Tim Wescott" <tim(a)seemywebsite.com> wrote in message news:r6ydnaZqRLr2aOjWnZ2dnUVZ_rZi4p2d(a)web-ster.com... > On Fri, 12 Feb 2010 19:01:46 -0500, Martin Riddle wrote: > >> "Vladimir Vassilevsky" <nospam(a)nowhere.com> wrote in message >> news:UqOdnWHSjYZDQOjWnZ2dnUVZ_gGdnZ2d(a)giganews.com... >>> >>> >>> Chris wrote: >>> >>>> I need to make a PLL that slaves to a 24Hz square wave. The output >>>> of >>>> the loop would be a 60Hz square wave. Any CMOS level chips that >>>> would >>>> be good for this? I understand that I would need to divide by a >>>> decimal value of 2.5 for the loop. >>> >>> Use a PIC. >>> >>> Lock on 24 Hz by input capture, generate 60 Hz by output compare. Do >>> all PLL logic in software. There will be a jitter of +/-1 timer >>> clock, >>> however this will be much better then suggested analog solutions. >>> >>> >>> Vladimir Vassilevsky >>> DSP and Mixed Signal Design Consultant http://www.abvolt.com >> >> Hi Vladimir, Is there good reading references for doing a software >> PLL >> anywhere. >> So far in my casual searches, I've found very little on a software >> implementation. > > No, but here you go. This will be a complete document, with > introduction, discussion, analysis, and a conclusion: > > Making digital PLLs in software is fun and easy (introduction). > > They're just like hardware PLL's (discussion) > > except where they're different (analysis). > > But they're easy, if you think hard. So go do it! (conclusion). > > Was that too terse? > > -- > www.wescottdesign.com Sort of. Thanks Cheers
From: MooseFET on 12 Feb 2010 21:38 On Feb 12, 2:14 pm, Chris <christopher.man...(a)gmail.com> wrote: > I need to make a PLL that slaves to a 24Hz square wave. The output of > the loop would be a 60Hz square wave. Any CMOS level chips that would > be good for this? I understand that I would need to divide by a > decimal value of 2.5 for the loop. How accurate is the 24Hz? How good does the 60Hz need to be? You can take a crystal and divide it down to make the 60Hz and then make the counters get reset at a 12Hz rate to force it to be in step. An HC4046 will lock in just a couple of cycles if you use the edge operated phase comparator. You can multiply up to several hundred Hz to make the component values for the oscillator more reasonable.
From: MooseFET on 12 Feb 2010 21:39 On Feb 12, 2:48 pm, "tm" <no...(a)msc.com> wrote: > "Spehro Pefhany" <speffS...(a)interlogDOTyou.knowwhat> wrote in message > > news:eilbn5pphbtca65k6aqjge9ddtenoumf1l(a)4ax.com... > > > On Fri, 12 Feb 2010 14:14:04 -0800 (PST), Chris > > <christopher.man...(a)gmail.com> wrote: > > >>I need to make a PLL that slaves to a 24Hz square wave. The output of > >>the loop would be a 60Hz square wave. Any CMOS level chips that would > >>be good for this? I understand that I would need to divide by a > >>decimal value of 2.5 for the loop. > > >>Thanks, > >>Chris Maness > > > You could phase lock the 24Hz (movie frame rate?) to a 120Hz VCO > > divided by 5, and divide the 120Hz by 2 to get 60Hz. > > Or divide the 24 Hz by 2 and lock a 60 Hz PLL to the 12 Hz by a divide by 5. > > Same thing but your soln. has higher frequencies so smaller caps. In PLLs it is better to multiply up first then down.
From: MooseFET on 12 Feb 2010 21:41 On Feb 12, 3:01 pm, Vladimir Vassilevsky <nos...(a)nowhere.com> wrote: > Chris wrote: > > I need to make a PLL that slaves to a 24Hz square wave. The output of > > the loop would be a 60Hz square wave. Any CMOS level chips that would > > be good for this? I understand that I would need to divide by a > > decimal value of 2.5 for the loop. > > Use a PIC. > No, the 8051 is the right processor for this. [ducks]
From: Jon Slaughter on 12 Feb 2010 23:34
Martin Riddle wrote: > "Vladimir Vassilevsky" <nospam(a)nowhere.com> wrote in message > news:UqOdnWHSjYZDQOjWnZ2dnUVZ_gGdnZ2d(a)giganews.com... >> >> >> Chris wrote: >> >>> I need to make a PLL that slaves to a 24Hz square wave. The output >>> of >>> the loop would be a 60Hz square wave. Any CMOS level chips that >>> would >>> be good for this? I understand that I would need to divide by a >>> decimal value of 2.5 for the loop. >> >> Use a PIC. >> >> Lock on 24 Hz by input capture, generate 60 Hz by output compare. Do >> all PLL logic in software. There will be a jitter of +/-1 timer >> clock, however this will be much better then suggested analog >> solutions. Vladimir Vassilevsky >> DSP and Mixed Signal Design Consultant >> http://www.abvolt.com > > Hi Vladimir, Is there good reading references for doing a software > PLL anywhere. > So far in my casual searches, I've found very little on a software > implementation. A simple and straightforward method: for(i = 0; i < N; i++) if ((i + k) % M == 0) recompute k, toggle clock; Choose N, k, M appropriately. The loop is synched to the first clock. This method only works when increasing the clock speed but has a similar method for the opposite case. If N can be appropriately chosen then k can be set to 0. |