FPGA
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Power Management for PCIe hi I am implementing BMD design as explained in xapp1052(v2.5). Have implemented the design on Avnet V5LXT/SXT PCIe Development Board using the PCIe. Have generated the Endpoint Block plus for PCIe 1.9 using ISE 10.1. I have been successful in running the BMD design. I want to switch off the power management at ... 14 Jun 2010 04:04
Altera Quartus - how to create small roms & rams for Cyclone 3 Help !!! The megawizard in Quartus 2 does not seem to support generating small roms & rams using the LUT tables, only using the M9K memory blocks. Any way to generate small roms & rams using the logic cells ? I'm looking for something similar to Xilinx distributed memory generator. TIA. Jim ... 14 Jun 2010 19:35
Prog4 - Altera Programming Cable and a development board in one. In prep for the release of more Altera development board additions to our range we have a new programming cable Prog4. We will be selling this 2 ways. The first is as a programming cable and that will be in a case similar to our Xilinx cable Prog3.. The second use is as a simple FT245 USB based development board ... 15 Jun 2010 15:22
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how to interface a ddr2 memory controller to a processor hi all, i have a ddr2 controller that works on 4 burst mode. ddr2 dq width is 16. i must provide 2, 32 bit data to the controller before writing it to memory. As well as when reading from a memory location it gives out 2, 32 bit data out. my processor is a master AHB, has a 32 bit address and 32 bit data bus. ... 11 Jun 2010 12:32
Is it possible to get consistent implementation results? Hi, I'm working with Xilinx ISE 10.1 and I am having troubles with timing constraints. I've successfully implemented my design with a 20 ns cycle time and found that I needed to change something in the design. I make my changes and re-synthesize and implement design and I no longer meet the same timing constra... 12 Jun 2010 05:00
Alternative to Chipscope I would like to have capabilities of Chipscope for Xilinx FPGA's are there any free alternatives to it? a.t ... 11 Jun 2010 08:06
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Design passes synthesis and routing but fails on FPGA Hi, I'm somewhat familiar with synthesis and Verilog but I am quite new to running the designs on FPGAs. I have a complex design of a processor that I am trying to get running on a Virtex 5 FPGA in a BEE3 module. The design synthesizes and goes through translate, map and par in Xilinx ISE 10.1 but it does not seem t... 10 Jun 2010 07:46
How to Disable IP Core after Evaluation Period Hi Guys, I am just wondering if there are any standard ways of disabling an ip core after an evaluation period of say 30 days. I am trying to provide a potential customer a ip core but don't want them to continue using it after the eval license period expires. The core will run on Xilinx Spartan3 FPGAs. Any ... 10 Jun 2010 03:26 |