FPGA

error in XPS
Checking expanded design ... ERROR:NgdBuild:604 - logical block 'mult_ipif_0/mult_ipif_0/USER_LOGIC_I' with type 'user_logic' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, or the misspelling of a type name. Symbol 'user_logic' is not supported in target 'spart... 29 Jun 2010 15:10

Require a solution - LVDS support +RJ45 connectors
Hello, I am not sure if this post is in the right place - I hope to get some help I am looking for a PCI/e based FPGA solution - The board should be able to support LVDS with 2 RJ45 i/o ports which connect to CAT5 cables. I plan to implement SPI signal on the FPGA and send the generated signal over LVDS. I am ... 29 Jun 2010 15:10

MicroBlaze - how to instantiate/connect more BRAM to the LMB
Hi, I am working on the creation of MicroBlaze. I am able to generate single BRAM of 64 KB. I would like to have many BRAM (say 4) each of size 8KB connected to the LMB Bus of the MicroBlaze. Can anyone explain how to do this. Thanks Vivek --------------------------------------- Posted thro... 30 Jun 2010 09:44

Using Xilinx TFT controller IP for normal VGA port on Spartan 3E 1600 ?starter Kit
Manmohan <mmmmec(a)gmail.com> wrote: I would like to incorporate into my design a VGA controller . For this purpose, I am planning to use the Xilinx XPS TFT controller IP which has the VGA signals included in it. However, the issue is this IP has 6 bit width for each of the three colour components . Howeve... 29 Jun 2010 03:04

Using Xilinx TFT controller IP for normal VGA port on Spartan 3E 1600 starter Kit
Hi all, I would like to incorporate into my design a VGA controller . For this purpose, I am planning to use the Xilinx XPS TFT controller IP which has the VGA signals included in it. However, the issue is this IP has 6 bit width for each of the three colour components . However, the normal VGA port uses only ... 29 Jun 2010 03:04

Altera Stratix4GX PCIe card as a root-port
I wanted to know if anyone has used the Altera Stratix4GX PCIe card as a root port. I have used it as endpoint but have not used as a root- port. As an endpoint all I have to do is plug in the card to a motherboard. But as a root-port, it needs to send out the requests to end point. ... 28 Jun 2010 16:08

help with OVL on Actel tool
Hi, I am a verilog designer and I'd like to try OVL on an Actel design. I can't figure out how to use the OVL library. I downloaded it, but in the Actel Libero tool I can't find any way to add a path to the library. So if on my verilog code I put a OVL assertion, it will be flagged as an error by the Actel "Ch... 28 Jun 2010 19:27

Free bitmap font
I want a simple bitmap font to use in my project. I'm looking into using a 80x25 or 80x24 format. Where can I get a font like this in an easy format to incorporate into my project? ... 27 Jun 2010 07:23

Call for Papers Reminder (extended): World Congress on Engineering and Computer Science WCECS 2010
Call for Papers Reminder (extended): World Congress on Engineering and Computer Science WCECS 2010 CFP: World Congress on Engineering and Computer Science WCECS 2010 Draft Paper Submission Deadline (extended): 16 July, 2010 Camera-Ready Papers Due & Registration Deadline: 30 July, 2010 WCECS 2010: San Francisco,... 26 Jun 2010 05:26

how to know that SRL16 was infered on xilinx?
Hello, I am implementing a core from xilinx (FFT) and wanted to know how the feedback shift registers are implemented. The xilinx core manual says that the earlier stages that need large shift registers uses Block RAM and other stages use distributed RAM. Does this mean it used SRL16s? How do the SRL16s show up... 25 Jun 2010 16:28