FPGA

Block RAM unusually long setup time ?
Hello, We are working on a project which involves using BLOCK RAMs. Since we were new to Block RAMs, I (my colleague actually) instantiated a BLOCK RAM in VHDL using Xilinx's Block RAM IP core. The question is regarding timing: The datasheet for the target Spartan 3ADSP XC3SD1800-4 device specifies the best... 3 Jun 2010 11:07

Xilinx' partition flow in ISE12.1
Hi *, has anyone had any success with the "new" partion flow in ISE12.1? I've been fiddling around with this for a few hours, but whatever I try, the design fails to even finish routing on the first pass as soon as I enable partitions. The error messages vary, mostly it's complaining about hundreds of unrou... 27 May 2010 03:48

Xilinx ISE12.1 IPCORE source code
1.the format of encrypted file can_v3_2/can_tl_bsp.vhd as an example. a)the first 8 bytes XlxV62EB is version code,From ISE11.1 Xilinx use AES. b)the first 8bytes of line2 is the length of the ciphertext.，it means that the next segment of ciphertext is after 3300H c)from 18h bytes is ciphertext which is made by... 27 May 2010 00:36

EDK BFM Simulation
On Apr 14, 1:05 am, "maxascent" <maxascent(a)n_o_s_p_a_m.n_o_s_p_a_m.yahoo.co.uk> wrote: OK thanks I will take a look at the zip file but UG254 seems quite old so I'm not sure if this is the files I need. Jon         ---------------------------------------         Posted throughhttp://www.FPGARelate... 26 May 2010 20:15

Help (Virtex 155 and 220 compatibility) !
I had a board which mounted Virtex 155. I've changed the FPGA to Virtex 220. The support engineer of Xilinx sales company said both FPGAs were compatible and there was no problem. But all 4 board I changed FPGA don't work at all. Even JTAG interface doesn't work. Are they actually compatible? Or do we need to mo... 26 May 2010 14:40

Using XMOS devices to replace FPGAs
Here is a nice paper showing how XMOS devices can replace FPGAs in many applications: http://www.xmos.com/system/files/wp-xmos-fpga.pdf Leon ... 27 May 2010 14:48

crc16 with 16 bit inputs
Hello, I am trying to implement several crc generator/checkers in vhdl in an fpga. The crc32 seems to work ok, a byte at a time. Can I do crc16 16 bits at a time, rather than a byte at a time? Thanks. Bill --------------------------------------- Posted through http://www.FPGARelated.com ... 27 May 2010 23:37

BRAM with output register using ram_style attribute
On May 25, 7:47 pm, "shantesh" <shantesh84(a)n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote: Hello, I'm curious to know if there is a way we could tell the synthesizer to use registered mode of BRAM when using ram_style "block" attribute. The registered mode otherwise can be enabled by instantiating a BRAM w... 26 May 2010 06:57

BRAM with output register using ram_style attribute
Hello, I'm curious to know if there is a way we could tell the synthesizer to use registered mode of BRAM when using ram_style "block" attribute. The registered mode otherwise can be enabled by instantiating a BRAM with DOA_REG, DOB_REG set to 1 and REGCEA, REGCEB set to '1'. For example, the VHD... 25 May 2010 20:08

Software bloat (Larkin was right)
On Tue, 25 May 2010 06:38:05 -0700, MooseFET wrote: Switching to Altera looks to be safe to do. I haven't designed in any of their parts lately so I won't have to warn you away from any of them. I'm quite fond of them. My first "proper" FPGA devkit was a DE1 (bought mainly because it had a good price-perf... 4 Jun 2010 09:11