FPGA

Error:Place:645 on a non-clock pin.
Hello, I have an EDK 11.1 project with a single custom peripheral containing exterior ports. After assigning said ports in the .ucf file to buttons on my FPGA board (for debugging purposes), I can generate the netlist but I receive the following error when I try to generate the bitstream: "Error:Place:645 - A... 23 Nov 2009 12:57

Too Easy: Actel FPGA's! :)
5 minutes video http://www.youtube.com/watch?v=hnmSJJOD86A from vhdl to the programming files, and programming without actel programmer using DirecC and usb-jtag cable Antti PS i messed up alter-actel in the video a few times :( ... 18 Nov 2009 00:11

Altera Stratix IV GX Dev.Kit: PCI-E x4 device doesn't work in x8 slot
Hi We have a problem with Altera Stratix IV GX FPGA Development Kit. Specifically, we build a PCI Express design based on Altera's own "hard" PCI-E core configured for Gen.1 x4 operation. The design works (more or less, but that's behind the scope of this message) when it is plugged into x8 mechanical/x4 electrica... 1 Dec 2009 19:32

Drigmorn2 - Spartan-3A Board
Having just done on gigantic Merrick1 with it's 101 FPGAs we thought we would do a small board this time. Drigmorn2 http://www.enterpoint.co.uk/drigmorn/drigmorn2.html is aimed at student lab and the small end industrial controller type markets. It's MicroBlaze friendly with 128Mbit SPI Flash and 256Mbit of SDRAM. ... 13 Nov 2009 11:00

max. sinking current of XC95144xl cpld
nishad, Why do you doubt? If the data sheet says an IO may sink 8 mA, then why not ALL IO at 8 mA? No problem. The only concern here is ground/Vcc bounce: yes, 128 * 8mA is a lot of current, and you should make sure your pcb has good power and ground planes, and the recommended bypass capacitors. Austi... 13 Nov 2009 00:04

Altera/EPCS16 issues
Hi, On a board here I always load an EPCS16 without errors, and the FPGA (cyclone III) works as expected. But Quartus II it does not verify the EPCS16 it reports operation failed. However yesterday I had it verifying ok for more than 2 hours and today if fails again to verify. All other operations seem to w... 12 Nov 2009 10:35

Ethernet PCIe boards and PHY daughter cards?
I'm interested in a development board that supports dual gig ethernet PHYs and PCIE (or perhaps PCI-X). As part of that I'm also interested in 10/100/1000 daughter cards. I've seen the following boards (mostly from http://www.fpga-faq.com/FPGA_Boards.shtml): http://www.knjn.com/FPGA-PCI.html I've bought ... 12 Nov 2009 07:16

Having trouble with Xilinx timing constraints
Hello all, I have having trouble figuring out how to properly define some timing constraints for an interface between two Xilinx Virtex-4 LX100's. If anybody has any insight on the best way to solve this problem, it would be appreciated. Here are the fixed system parameters (these cannot be changed no matter... 16 Nov 2009 18:01

order
hi group, In following page, in what order should I start to learn about Virtex 4 ? http://www.xilinx.com/support/documentation/virtex-4_user_guides.htm Thanks, Amit ... 10 Nov 2009 11:48

Serial interface between PC and FPGA using matlab
hi all. i am using Spartan 3A DSP 1800A board which supports a UART/serial link. when using EDK i can directly use it to send the data from the FPGA to the PC using the xil_printf() command which i can finally view in hyperterminal.But now i want to send the data from FPGA to matlab instead of hyperterminal. I am... 9 Nov 2009 12:09