FPGA
in [Hardware]
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fsm coding question This is in Altera cylone-3. I have this code which seems to run OK in RTL and gatelevel simulation but I m getting glitches in signaltap and in oscilloscope. The clock is running at 100 MHz but data is being written and read from a Ram every 5 us or so. I am getting glitches in State 2 and 3. The STATE... 29 Dec 2009 05:20
Call for Papers Reminder (submission deadline extended): International MultiConference of Engineers and Computer Scientists IMECS 2010 CFP Reminder (submission deadline extended): International MultiConference of Engineers and Computer Scientists IMECS 2010 From: IAENG - International Association of Engineers Draft Manuscript submission deadline (extended): 12 January, 2010 Camera-Ready papers & registration deadline (extended): 30 January, 201... 28 Dec 2009 02:04
Info on heritage Nallatech board? hi folks, I have a very elderly Nallatech Strathnuey board that I might try to get going if I have e few spare hours. It has two old-original Spartan XC2S150 devices, two Xilinx flash ROMS, a USB interface and a bunch of power regulators; it also can plug into a PCI slot (I probably won't try to use that) and... 28 Dec 2009 09:38
More details: VHDL: assignment to two different fields of the record in two different processes As enticing as it is, I've found that using record types in synthesizable VHDL is just inviting problems. I certainly wouldn't do it if I needed separate processes to drive different elements of the record. Avoiding 'Z' except for actual tri-state hardware (e.g., IOB pins on FPGAs) is a good idea. The synthesi... 1 Jan 2010 03:19
Xilinx and Multi-port memories I'm trying to build a register-file for an ALU which has 3 read ports and 1 write port. There is a single clock design but I need to assume that all ports are in use on every clock cycle, worst case. I can envision implementing this using 3 Dual Port Memories each with one read port and one write port as fo... 2 Jan 2010 12:46
More details: VHDL: assignment to two different fields of therecord in two different processes I have found the following discussion: http://www.velocityreviews.com/forums/t487026-vhdl-port-inout-problem.html And according to the solution decribed there, I set ALL fields (elements) of the record in ALL processes. If the particular process does not drive the particular signal, I set it to "Z". This sol... 25 Dec 2009 17:58
Altera FPGA configuration using JTAG Hello, I want to configure an FPGA (Altera Cyclone II) using JTAG programming method via USB. I have done a design using a PIC18F2550 and succedded in configuring Xilinx FPGA. I want to do the same thing fo Altera devices. Has anybody done that previously? The point where I am stuck is, I don't know the internal ... 25 Dec 2009 08:15
H.264 on Spartan3A DSP Hi all, I am building a new megapixel camera based on Spartan3A DSP 3400. For one of the applications I would need H.264 core with a performance of minimal 66Mpix/s. I prefer EDK HW core since the camera "brain" is composed there. Does anyone has anything to recommend? Best regards, Ales ... 23 Dec 2009 10:49
Please help, Xilinx FIFO problem! I hope my plea will not be seen as usual "please help me" request. I do my (home)work, I try hard but sometimes there come up problems that seem very hard to solve, with the current problem, well if there is no solution to that, then I wonder how come it has been ever been possible to use Xilinx FIFO's with problem... 23 Dec 2009 13:36 |