FPGA

Last Call for Papers Reminder (extended): IAENG International Conference on Control and Automation (ICCA 2010)
CFP Reminder (extended): IAENG International Conference on Control and Automation (ICCA 2010) From: IAENG - International Association of Engineers Draft Manuscript submission deadline (extended): 12 January, 2010 Camera-Ready papers & Pre-registration deadline: 30 January, 2010 ICCA 2010: 17-19 March, 2010 http... 2 Jan 2010 05:14

Hal Murray stillon this list
Hi If Hal is still on this list can he contact me, re TMS roms etc swchuck(a)gmail.com Thanks Charlie ... 1 Jan 2010 17:22

verilog multiplexer
I would like to create a generic multiplexer in Verilog were I can set the number of inputs and data bits. I can create something using 2 input multiplexers cascaded but this produces a priority structure which uses more logic resources. If anyone can give me a clue as to if it is possible that would be great. Jon ... 2 Jan 2010 06:18

International Journal of Electronics, Information and Systems (IJEIS) Call for Paper
International Journal of Electronics, Information and Systems (IJEIS) Call for Paper The International Journal of Electronics, Information and Systems (IJEIS) publish original papers on all subjects relevant to electronics, computer science, communication network, and information systems. The highest priority will... 31 Dec 2009 08:46

XILINX license model restricts longtime availability
>On May 15, 4:00=A0pm, John McCaskill <jhmccask...(a)gmail.com> wrote: Xilinx has switched to using FlexLM for licensing as of ISE 11.1. =A0I have been using multiple other software packages that use FlexLM for years, so I have some experience with the issues that it can cause. FlexLM is more restricti... 30 Dec 2009 16:28

ADC problem on spartan3E
Hello I wrote a vhdl code for implementing amplifer and ADC on sparan3E board, I am working with LTC1407A-1 Dual A/D on spartan3E(with SPI protocol),my problem is when I changed the analog voltage which is applied to this A/D,the eight most significant digital value on LEDs also changed accordingly,but it's not... 7 Jan 2010 09:02

VHDL: assignment to two different fields of the record in two different processes
On Dec 25, 4:53 pm, wzab <w...(a)wzab.nasz.dom> wrote: To simplify design of the DSP system I have decided to describe the ports connecting different blocks (to be synthesized in the same FPGA) as a record. It resulted in a code, in which two different processes (each in one of connected blocks) assign val... 30 Dec 2009 10:53

ACE file programming of Virtex 4
i have a cypress fx2lp usb2 that emulates an ACE hdl player and outputs the Jtag directly to an XCF32P and an SX55. there are a couple of issues i am still not sure about though, 1- on a TDO check, the ace file gives me the output data for TDI, a mask, and an expected return value. The SX55 and XCF32P have a... 30 Dec 2009 14:14

Seeking some advice
Rick wrote: I want to get back into some 'trivial' design work. I'm thinking my level of sophistication is still at the ~22v10 stage and using schematic capture vs. programming languages or assembler. I have read enough to know this is bad form but I still understand 74LSXX and would like to ease into ... 31 Dec 2009 09:51

How to protect my Virtex5 design without battery?
For certainreasons, I could not use battery on my board, so the Virtex5 bitstream encryptioncould not be used. In this situation, what could I do to protect my design on areasonable level? My design hasVirtex5 and XCF16P, and the two devices are linked on JTAG chain, and I programXCF16P with my design through JTA... 6 Jan 2010 08:27