FPGA
in [Hardware]
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CPLD/FPGA with Linux Hi, I have just started out with some VHDL in school and would like to have something at home to play with. I'm not sure of CPLD vs FPGA for my use, but CPLD feel more suited for smaller projects I guess. My question is how Linux is supported as developmentplatform? (I have linux on my computers at home and want to... 25 Oct 2009 17:35
EDK/DDR Problem with HTG-V5-DDR3-PCIE Development Board Howdy All, I have a HTG-V5-DDR3-PCIE-FX100 development board. It comes with custom XBD file, but I am having troubles using the DDR2 memory. (It has both ddr2 and ddr3 memory). The I try to compile it I get: ERROR:MDT - issued from TCL procedure "check_partno" line 21 DDR2_SDRAM (mpmc) - The parame... 21 Oct 2009 05:59
EDK/DDR Problem with HTG-V5-DDR3-PCIE Development Board Howdy All, I have a HTG-V5-DDR3-PCIE-FX100 development board. It comes with custom XBD file, but I am having troubles using the DDR3 memory. The I try to compile it I get: ERROR:MDT - issued from TCL procedure "check_partno" line 21 DDR2_SDRAM (mpmc) - The parameter C_MEM_PARTNO=EBE52UD6AJUA-6E-E ... 21 Oct 2009 05:59
Spartan-3A DSP and include a Digital Clock Manager (DCM_SP) - How to do it? I have ISE 11.1 and the DCM does exist in the coregen for this release. Is it not in your version of coregen or is it grayed out? Your image doesnt seem to work. Jon --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.com ... 20 Oct 2009 13:21
Dealing with SPI ADC timings I'd like to implement an SPI master to read an AD7924 ADC. The thing is that there are some setup and hold time I have to respect, ie CS'to SCLK setup time, SCLK to DOUT valid hold time, etc. They go from typically 10 ns to 50 ns. What's the best way to implement these delays? ... 20 Oct 2009 14:28
Spartan-3A DSP and include a Digital Clock Manager (DCM_SP) - How to do it? Dear All, I have a Spartan 3A-DSP 3400A board http://www.xilinx.com/products/devkits/HW-SD3400A-DSP-DB-UNI-G.htm and a licence for the ISE System Edition. I am trying to implement the simple stop watch tutorial at page 19 of the ISE In-depth tutorial at here: http://www.xilinx.com/support/documentation/sw... 21 Oct 2009 11:28
xilinx edge trigger interrupt Hi, I am trying to implement an interrupt handler which only interrupts on the rising edge of a gpio signal. So far, it always interrupt regardless of input signal, rising or falling. here is my MHS snippit BEGIN microblaze PARAMETER INSTANCE = microblaze_0 PARAMETER C_INTERCONNECT = 1 PARAMETER HW_VER = ... 20 Oct 2009 12:14
How to inspect values in a Xilinx core FIFO with Modelsim? Hi, trying to debug a design and look for a way to inspect the actual data that are inside a FIFO which has been generated with the core generator. I have turned off all optimization in order to see process variables etc., but all I find is a lot of control signals and generics. I looked into the behavioural code ... 19 Oct 2009 09:41
License issues The dreaded License expiration has bitten me in the butt again. I don't recall if I had this exact same problem before, but I am pretty sure I was told at one point that my tools would not expire when maintenance ran out, because that is what is stuck in my head. However, that is not the case. My copy of ispLever... 21 Oct 2009 12:36 |