FPGA

Goal to make $30-40 Open Source Logic Analyzer with Spartan 3E.
Hello, We are working on a project to create a low cost Open Source Logic Analyzer. We are making great progress but would greatly appreciate any input from members of the comp.arch.fpga group. The design is based on the following resources: -Sump Logic Analyzer VHDL design. (http://www.sump.org/projects/ ana... 1 Dec 2009 12:44

Virtex 5 ISERDES
I am looking at using the ISERDES block in a V5 design for a DDR2 controller. I want to input the DQ into an IODELAY block and then into the ISERDES. Problem is I am not sure that you can do this anymore. I have seen some old app notes with this configuration and a DDLY input on the ISERDES. But the new user guides... 24 Nov 2009 04:29

Spartan6 PCIe and multiboot
Hi! I am designing a system that needs PCIe and multiboot operation. I would like to be able to reprogram the application FPGA at any moment. The safest option would be using a GN4124 and any FPGA. That would be clean and simple. But if you think of PCIe and multiboot then using a single Spartan6 comes out as t... 26 Nov 2009 04:15

EDK11 under 64-bit OS
ISE/EDK11 has been crashing on me lately relentlessly complaining about the lack of memory and just for no reason. I am considering moving to a 64-bit OS just to eliminate the memory issue although I believe the root of the problem is in the tools. Anyways, I was just wondering if the latest EDK is indeed fully... 23 Nov 2009 12:57

FPGA + Ethernet
Hello I have to send and receive some data through ethernet, try to make a transceiver. I found the LAN91C111 to save me from writing the part of layer 2 (MAC). Does anyone have any example in VHDL or Verilog how to send and receive data with the integrated layer 2?. I'm new to fpga and do not really know how to... 21 Nov 2009 20:19

IP core for Bluetooth or Wifi
Hi, Somebody know where can I found a free IP core for Bluetooth or Wifi? I would like to use it. I don't mind use a USB or UART module. Best. ... 19 Nov 2009 11:40

TimingAnalyzer -- Build Timing Diagrams directly from VHDL or Verilog
On Nov 18, 11:12 pm, timinganalyzer <timinganaly...(a)gmail.com> wrote: Hi All, The latest version of the program is beta version 0.945.  Python scripting,  improved GUI zooming, and logic function simulations have been the focus in the 0.94X series An application note on the website shows how to aut... 19 Nov 2009 10:32

AvalonST to Avalon MM Bridge
For Altera Straix4 GX FPGA, Is there a bridge module available between the Avalon-ST to Avalon-MM? Trying to use the PCIE endpoint hard IP using Altera Megawizard software. But this interface generates the Avalon streaming output. I think for what I am doing I do not need very high performance bus and Avalon-MM ... 20 Nov 2009 20:10

LDPC FADING
I simulate LDPC code over AWGN channel I need to simulate over fading channel How implement fading channel in matlab ? ad what is the modification require in my code ? ... 23 Nov 2009 11:50

Fast stratix3 JTAG programming?
I wonder if anyone have experience with this. I want some HW that can compete with the serial flash programming speed. Maybe some kind of usb-io pre-programmed microcontroller that can run at full speed. Will any of the available blaster HW's be able to run at full speed if integrated close to the fpga? ... 20 Nov 2009 06:44