FPGA

Picoblaze bit file block ram remplacement
Hi everyone, I've been playing with fpga since a couple of time and I can't find the answer to my quesiton. I have a picoblaze in a design of mine and I want to update the bitstream without having to re-"build" my design entirly ( to save time ). I'm using linux and thus the tool given with the picoblaze can't ... 4 Dec 2009 15:07

Problem with Xilinx ISE and Spartan3
As a beginner in FPGA design I run to the following problem: I want to generate a 200MHz clock by the DCM from 2 different clock sources, one is a 10MHz clock, the other is 60MHz. My idea was to divide the 60MHz by 6 and alternatively switch between the both clock-signals. I use the Xilinx ISE9.1 and a Spartan3.... 24 Dec 2009 18:23

Where to go when Spartan-3A DSP 3400 is full?
Hi, Just got a question what to do if future needs fill up a Spartan-3A DSP 3400 CS484. A very quick and unqualified look at Spartan-6 family show a package called CSG484 with same physical dimensions as the CS484. Hope to do as few changes on the PCB as possible. Since the supply voltage is not the same, a drop-i... 4 Dec 2009 12:51

Does Xilinx sync FIFO use dual port memory? Does this affect resource?
Hi, When using a synchronous FIFO, it seems like one can read and write into the FIFO at the same time. Does this means that the underlying memory is a Dual-Port blockram? If so, what is the cost of using such a dual port memory in a Xilinx FPGA. My experience is with ASIC, where most dual-port memory are abo... 3 Dec 2009 14:50

Xilkernel interrupt test failure.
Hi all, I'm developing an FPGA (V5SXT50) containing a microblaze core. I have a problem that I do not understand how to find a solution. If I set the Software Platform Setting to use a standalone OS, all seems to work fine. The test applications (memory test, peripherals test ...) do not give me any errors. If I s... 3 Dec 2009 08:06

domain crossing and clock synchronisation for a high frequency timer
Hi, After all the clock generation stories, now comes the time of time counting. So I want to implement a high-frequency (<=100MHz ?) counter/timer that gets incremented by an auxiliary input, and the problem comes from the clock domain crossing : the low-frequency "acquire" signal must latch the counter in ano... 23 Dec 2009 13:37

This works, this does not... why?
I have two CPUs (master and slave) and a Spartan II FPGA. CPUs communicate using FPGA. Inside the FPGA there is a READY flag which: - master can reset to '0'; - slave can set to '1' or to the state of another flag; - also, hardware RESET can reset it to '0', but that never happens; So, READY should be im... 5 Dec 2009 19:32

PMC or XMC based on Altera parts (preferably Stratix)
Hi, On a project requiring intensive processing based on VXS boards we are looking at ways of increasing the processing power by using a mezzanine board hosting a large FPGA with fast access memory resources. The mezzanine would preferably be an XMC type and PMC as a last resort. We are looking for an Altera bas... 1 Dec 2009 17:15

vga in virtex 4
I am an electronics student and pretty new in FPGAs' use. I am interested in to send images to a monitor from the FPGA. I have already performed a test using the Spartan 3 xilinx board based on an example I found at the Internet and it worked perfectly. Now I am trying to translate the same example to the ML405 xi... 28 Nov 2009 12:19

Initializing color bars on CH7301
I'm working with a xilinx virtex 5 board (with the VLX110T) and have been trying to get any kind of output to a DVI monitor. I'm using the IIC core in XPS to try and program the CH7301. I'm using a clock generator to send a 25MHz clock to the xclk pin, sending a high value to the xclk*, and not sending any of the 12 da... 13 Dec 2009 21:58