FPGA
in [Hardware]
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Add custom Ip to EDK - No result from sw registers Hello there, I'm adding custom IP (DCT core) to EDK 9.1. Input (xin) is write to slv_reg0 while output (dct2d_out) is write to slv_reg1. I'm following a tutorial from http://www.ee.cooper.edu/~stefan/projects/tutorials/edk_custom_ip/edk_custom_ip.pdf I can write and read from the slv_reg0 (for input, xin), b... 7 Jan 2010 06:50
PMC or XMC based on Altera parts (preferably Stratix) Hello JF, I recommend that you take a look at http://www.parsec.co.za/pm432.php Best Regards, --jmv ... 7 Jan 2010 05:44
A VHDL compiler error report in Xilinx ISE 10.1 and service pack 3 without response Hi Xilinx, Here is the error reporting with its code and compilation result with ISE 10.1 and service pack 3. The code is specially simplified to highlight the VHDL compiler error characteristics. There are global data array definitions. when one of many data in the global data array is accessed in one logic lev... 6 Jan 2010 11:52
university platform cable Hello everybody, can anyone tell me what is the difference between the University Platform Cable (UW-USB-II-G) and the Platform Cable USB II (HW-USB-II- G)? There is almost no search result on the university platform cable, however it is present at more webshops about half of price as platform cable USB II. Has... 4 Feb 2010 14:33
Why are my pins being removed? LIT:243 and MapLib:701 warnings I'm working on a ML402 (Virtex-4) EDK project which has one custom IP ("event_getter") that was created using the EDK Create Peripheral Wizard and then I added my code (included below) to the generated user_logic.vhdl file. I am able to generate a netlist without issue, but when I compile the bitstream, I get the f... 7 Jan 2010 19:11
What a photon really is: What a photon really is: http://www.amperefitz.com/phton.htm Click link above Fitz ... 9 Jan 2010 10:43
Digital-to-Analog Converter LTC 2624, Spartan-3A Hello I am trying to write a vhdl code for DAC2624 on spartan3E,but I don't know how much I have to consider for SPI_SCK,should it be the same as my main clk which is 50Mhz? I wrote a vhdl code for ADC1407_1 and amplifier6912_1 on partan3E , I considerSPI_SCK to be 1Mhz in there ,but I don't know aboy DAC?sho... 4 Jan 2010 04:49
Cable autodetection failed A common problem with USB to parallel port converters is they don't work. You will find many previous postings on this. Sometimes a Cardbus or Expresscard plug in parallel port will work but many laptops don't even have these. Some docking stations can offer a parallel port option and we can use the Xilinx and our ... 6 Jan 2010 08:27
[Digilab IIE board]Cable autodetection failed Hi, I am using ISE 9.1 I had an old Digilab IIE board which i want to use. The Digilab IIE board can be programmed using the PC's parallel port. However, my PC has only USB ports. as such i bought an usb-DB25 cable to connect the parallel cable which comes with the board to my PC. Unfortunately when trying to... 2 Jan 2010 19:21
ASM hardware language definition file for Altera/Xilinx Hi, I need to write ASM hardware language for circuits. I wrote a lot about 10 years ago for Altera chip. Now I couldn't find the ASM hardware language definition file from Altera/Xilinx. Please help give a connection. Thank you. Weng ... 7 Jan 2010 23:35 |