FPGA
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Xilinx FIFO cannot be written Hello, i have a strange problem with my FIFO created with Xilinx CoreGenerator for a Spartan 3a. I have a FIFO with a read and write clock separately. The simulation of the design, including the FIFO signals are at this address: http://eech.org/fifoProblem.jpg After a wr_en and a Din and a wr_clk the empt... 21 May 2010 14:59
speed grade and temperature grade aren't marked?? I got this device XC4VLX80 but the speed grade and temperature grade aren't marked on a separate black row near the bottom. how do I know its speed and temperature grade? Thanks for your time! Jasmile --------------------------------------- Posted through http://www.FPGARelated.com ... 21 May 2010 12:47
Debugging SDRAM interfaces Hi guys, I could really use some help from an SDRAM / FPGA guru here... I've got an SDRAM controller IP core -- specifically, the sdram_wb core by Stephen Williams, available from the Git repository <git://icarus.com/~steve-icarus/sdram_wb.git>. This core works fine on the Altera DE1, with a 16-bit-wide 64Mbit... 24 May 2010 11:12
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Availability of XC6SLX16-2CPG196C Hello! Does someone know when this chips XC6SLX16-2CPG196C will be available on the market? On the www.avnet.com availability is 144 week. It's almost 3 years. What is wrong with that? Have you got any info about that? In the begining of this year I was informed that these chips will be on market, in Jul... 20 May 2010 06:12
FPGA Camp, Bangalore is tomorrow Final call for registrations to the 1st ever Camp in India. Register now visit http://www.fpgacentral.com/fpgacamp For registration just RSVP here & for more information visit http://www.fpgacentral.com/fpgacamp . For any queries email us at fpgacamp(a)fpgacentral.com FPGA Camp is the 1st and only open source FP... 20 May 2010 02:59
BLK_MEM_GEN_v2_8.I948.10 error when using BRAM Xilinx ISE 10.1 I am running a design using Xilinx ISE 10.1 on a 64-bit machine and after the compilation process I see this error in the ISIM window: Block Memory Generator data initialization complete. Signal SIGSEGV received ERROR: In process BLK_MEM_GEN_V2_8.I948.10 Signal SIGSEGV received This happens only on a 64-bit m... 19 May 2010 21:34
Problems inferring blockram in ISE12.1 Hi, I'm trying to tidy up the "sdram_wb" SDRAM controller IP core -- and my first target is its excessive use of device resources in the cache control logic. Specifically, it's setting up a 32x32 multi-port read/ write RAM which Xst doesn't recognise, and thus gets implemented as 1024 separate flipflops. This i... 19 May 2010 14:52
spartan6 configuration Hi all, In my Spartan6 board design, I want to use a Xilinx platform flash to configure it. My Spartan6 is a XC6SLX150 (32.2Mbits configuration memory) and the flash is a XCF32P (32Mbits). I' ve several questions : Is the flash big enough or should I have to use decompression option? How to program the f... 24 May 2010 00:27
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