FPGA

Synplify synthesis error
>Does it simulate OK? Sometimes the files need to be added in correct order, i.e. the file with the package must be added before any library units that make use of it. IIRC you can drag them around in the gui to alter the order, or check the .prj file which should have lines such as: add_file -lib work m... 23 Apr 2010 17:24

Virtex 7?
The CTO of Xilinx, during his keynote this morning at the Reconfigurable Architectures Workshop in Atlanta, made mention of the recent announcement of the Virtex 7 architecture. My colleagues and I assumed that either the announcement was very recent or not very well publicized as none of us had heard anything off... 23 Apr 2010 20:38

Xilinx Pipelined/Streaming FFT Architecure?
Hi, Can anyone tell me whether the Xilinx Pipelined FFT arch uses R2SDF or R2^2SDF? Regards, Onkar --------------------------------------- Posted through http://www.FPGARelated.com ... 23 Apr 2010 20:38

Raggedstone2 Spartan-6 Board Update
We have the Raggedstone2 in test now and expect to start shipping this board shortly. Picture of complete board is now on http://www.enterpoint.co.uk/raggedstone/raggedstone2.html. There should be some more support materials appearing over the next 1-2 weeks. John Adair Enterpoint Ltd. ... 20 Apr 2010 15:42

Efficient Multi-Ported Memories for FPGAs
Hi All, I've recently published a paper exploring how to implement memories with multiple read and write ports on existing FPGAs. I figured it might be of interest to some. Summary, paper, slides, and example code are here: http://www.eecg.utoronto.ca/~laforest/multiport/index.html There are no patents or o... 27 Apr 2010 21:18

clock routing to generic IO pins?
Hi, does anyone know if there is such a thing as clock IO for Xilinx FPGA?? If i were to design my own PCB board with an FPGA on it, do i necessarily have to route the clock from the on-board oscillator directly only to the clock IO pins? din consider this before, but thought i get some opinions to be sure ... 20 Apr 2010 15:42

Need to run old 8051 firmware
Hello all I need to run an old firmware for a Siemens SAB 80C537 microcontroller unit (MCU). The MCU is now obsolete (it's from the late 1980s). The firmware is compiled from several thousand rows of assembly language. It would take a long time to understand the code and re-program it in C. So ... 24 Apr 2010 12:46

Developin tool for Xilinx XC2018
Hello, what i need for programming,reading etc a XILINX XC2018 44PLCC ?What is the good tool? I need a toll for repairing old boards that have the XC2018 on board, Thanks ... 20 Apr 2010 15:41

Strange problem about Virtex-5 during working
hi all I have a strange problem during FPGA working.PROM files can be dowmloaded to Configuration flash XCF32P successfully,level of Dedicated configuration pins DONE and INIT_B is both high,FPGA works normally. But after a time FPGA can not works,level of pin DONE changes to be low!! level of pin INIT_B changes ... 20 Apr 2010 15:42

ReConFig 2010 : First Call For Papers
ReConFig10 2010 International Conference on ReConFigurable Computing and FPGA's December 6-8, 2010, Cancun, Mexico www.reconfig.org Conference Proceedings will be edited by the IEEE Computer Society Conference Publishing Services (CPS) and will appear at the IEEE digital Library. Authors of selected papers w... 20 Apr 2010 15:41