FPGA
in [Hardware]
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Expecting sequential output, but RTL shows concurrent implementation. Hi, I am trying to implement autocorrelation operation on an FPGA. Autocorrelation can be written as: Phi(n) = Summation { x(k) * x(n- k) } Essentially, the signal x(k) is multiplied with a delayed version of itself and the product is accumulated over a finite range of x(k) samples. I have written VHDL code,... 14 May 2010 19:23
repeting outputs of counter Hello, I am working on Vertex-5 and i have made a 20-bit counter. i have taken signal counter : std_logic_vector (19 downto 0) Output of the counter is monitored on scope with pre-specified pins. But surprisingly the output is first 8-bit showing proper counting and next 8-bit is similar to 1st 8-bit an... 9 May 2010 18:41
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Microblaze: Boot Program from SDRAM Hello everybody!! I spent 3 days on it without success and after it I decided to searching for an help. I have a Virtex-II system with Microblaze 7.10.d and external SDRAM memory. The hardware and software system correctly working and the usual "hello world" and "blinking leds" programs work properly. Since I... 8 May 2010 17:47
Floating Point Division Hello, I am trying to implement (simulation + synthesis) for 32bit floating point division unit. To perform division basically the 23+1bit (1 hidden bit) mantissa part is divided with the other mantissa, and then 8bit exponents are subtracted and finally normalization is applied. So for the mantissa division pa... 9 May 2010 02:29
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Xilinx FFT core -- Is varying precision through the core possible? Hi, Can I set the XIlinx FFT core such that the early (maybe first 5 out of 10) stages use smaller precision bits (same as input precision) --- and they use scaling. But the later 5 stages don't use scaling --- instead we allow them more precision bits. This will help me to use less precision (and hence less ... 6 May 2010 19:50
FPGA Compilation Time Windows vs Linux Hi, Does someone have some benchmarks comparing the compilation time between the Windows 64b and Linux 64b editions of the Xilinx ISE Design Suite? I need some arguments to invest in the right development platform. Many thanks. Eric ... 10 May 2010 10:56
Xilinx project failed timing constraints I am working on bit of a complex DSP design and generating .vhdl files based on the MATLAB/Simulink design. These vhdl files are then imported into a Xilinx project file and mapped, placed, routed, testing for timing to eventually generate a bit file for a Virtex SX95T. When I get a failed timing constraint, I manu... 6 May 2010 06:20
Signal name display in SignalTap Is there a way to get SignalTap to display just the signal name without the entire path? If the signal is deep within the hierarchy it's completely unreadable. ... 5 May 2010 13:45 |