FPGA
in [Hardware]
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Cheap FPGAs for tutorial Hi I wanna give some student a tutorial about FPGA programming and I wonder if there are any cheap FPGA evaluation kits out there that I could get? Needs to be nothing special, just a small board with some LEDS would be fun. THanks for any useful links, Andrew ... 3 May 2010 12:01
Synplify constraint problem I have a design in a Virtex 5 with an asynchronous fifo that has a write clock of 100 MHz and a read clock of 300 MHz. Both clocks are driven from a PLL. I want to tell Synplify that the two clocks can be in different clock groups for timing and so have a false path between them. However Synplify just looks at the inpu... 1 May 2010 16:29
Large Fanout Hi fellows, I have been working on a Virtex5 LX110 design using VHDL and ISE tools. My problem is that I cannot meet my timing constraints or the desired clock frequency. When I look at the timing report, I realized that the large delay is due to a signal with a large fanout. This has caused the delay to be domi... 30 Apr 2010 08:21
Spartan6 and 4GB RAM Hi, I' m new to FPGA and I want to design a board with a Xilinx Spartan6 FPGA and 4GB of RAM. Is it realistic to have a such quantity of RAM on a board? I suppose that there are design constraints to do it, is it easier to do it with DDR2 than DDR3 or others? The Spartan6 integrated memory controller only tr... 30 Apr 2010 09:27
Why hardware designers should switch to Eclipse Hendrik <hendrik.eeckhaut(a)gmail.com> writes: You misunderstood. The only absolute path is in the user interface. If That's my point. You have to change a path or do some operation. you move your project, you will also have to change parameters to point Emacs to the new location, be it a command line par... 29 Apr 2010 08:57
Virtex5 Aurora Hi, I am starting a new project using Xilinx Virtex5. I will be using the Aurora protocol for Rocket IO GTX interfaces. Plan is to use Xilinx ISE10.1. I am planning to use Xilinx's Aurora core from coregen. I will need to design a bridge to communicate to the Aurora link interface.I am new to using Aurora. If... 29 Apr 2010 06:44
Controlling the I2C master from Opencores.org >Hi, Is anyone aware of a design controlling the 'I2C_controller_core' from www.opencores.org? I read very good review of this core, but it needs to be controlled by either a state machine or a small processor. The current core only works at the 'byte' level. I'd like to be able to tell it: write those 3... 28 Apr 2010 11:41
xilinx arm finally announced http://press.xilinx.com/phoenix.zhtml?c=212763&p=irol-newsArticle&ID=1418796&highlight= years and years of talk, now going public :) Antti ... 30 Apr 2010 05:05
vhdl versus verilog This issue is frequently discussed on this board. I made a comparison and tested on VHDL and verilog using free simulators (GHDL and icaus). The test case was "to use a sparse memory model to reduce memory consumption. The idea is that a memory of large address (18 bits) of 16 bits data word consumes, only that muc... 28 Apr 2010 01:45
VHDL vs Verilog >hi, recently I read a quote about VHDL vs Verilog, along the lines of "VHDL is made by SW people who don't understand HW and vice versa"... Does anybody know the exact wording and origin ? yg -- http://ygdes.com / http://yasep.org One can see example between VHDL and verilog in the follow... 28 Apr 2010 00:37 |