FPGA

Xilinx no longer ships with Modelsim MXE?
I received a Sigasi Editor update email which had the following statement: "Xilinx no longer ships ModelSim with ISE but now ships its own HDL simulator that enables functional and timing simulations for VHDL, Verilog and mixed VHDL/Verilog designs: ISim." Is this correct? Although ISIM is not bad it is st... 23 Apr 2010 20:38

Quartus II under Windows7?
On Apr 21, 1:08 pm, Jon Beniston <j...(a)beniston.com> wrote: It's running ok for me on Windows 7 64-bit. What particular part of the software are you having problems with? Jon Well it installs alright, but Altium Designer 6 can't find it - whereas it did on my XP box. One problem is that Windows 7 lik... 23 Apr 2010 20:38

Custom IP with external ports
Hi I have a simple multiplier custom ip(the tutorial is easily found online). The tutorial created 3(internal) signals a,b and p. It multiplies a(16 bit) and b(16 bit) and sends the product to p(32 bit). It makes use of fifos(read fifo and write fifo). This works fine. But I am trying make p external. I chang... 23 Apr 2010 20:37

Polmaddie Family CPLD and FPGA Teaching Boards
On Apr 22, 3:59 am, John Adair <g...(a)enterpoint.co.uk> wrote: We finally made an assembly slot and built the 4 remaining Polmaddie CPLD and FPGA boards. These very low cost CPLD and FPGA boards will sell to universities and colleges in prices as low as $30-40. One off pricing starts at $60-70. The con... 23 Apr 2010 20:37

Absolute value of a two's complement number
The absolute value of an n-bit signed value is at most an n-bit unsigned value. (An n-bit unsigned value is an n+1 bit signed value.) Does your absolute value need to be signed? Ha this is what I was missing! Unsigned numbers still exist! Diego --------------------------------------- ... 23 Apr 2010 20:37

Problem with data2mem
Hi, The age old problem it seems data2mem and BMM files and I am stuck with a new problem I cant find the answer for. I have some generic ram in verilog which the xilinx software suite looks at and maps to two RAMB16s (higher two bytes and lower two bytes) so I have made a BMM file with the right names and widths ... 23 Apr 2010 20:37

How to over clock for DSP48
Hi, We are developing algorithm on a LYRTech ADC board. There are only 96 DSP48 on this board. We have a problem of DSP shortage with a FIR rcosine and low pass FIR design. There is a 105 MHz clock source with this board. I think a solution is to over clock DSP48 to improve performance. My question is how to doubl... 23 Apr 2010 17:24

Can Altera generate EDIF
Hi all, Can Quartus be persuaded to *output* an EDIF netlist of the design (at any point in the compilation)? Google returns lots of links about the EDIF import capabilities, but I can't see any on exporting! Why? I've started on an EDF reader for FPGAOptim so you can easily figure out what's going on with de... 23 Apr 2010 17:23

OFFSET and OFFSET out
Hi All, What is OFFSET In and OFFSET OUT ? Is it setup and hold time of Flip flop?. How to set a Offset in And offset out Constraints for a particular design? In synthesis report I'm seeing Minimum Input arrival time and Max.Output required time? whether it is equivalent to Offset in and Offset out ? ... 23 Apr 2010 23:17

confusion with ADC/DAC interface implementation
Hi, i am confused regarding the ADC/DAC interface implementation on FPGA. I have read a code where after serialising the input data of 16 bits in 16 clock cycles, the interface logic loops (in vain?) for another 16 cyles before serialising the next data. can#t understand why? why the serialisation of the next dat... 27 Apr 2010 01:02