FPGA

rtl simulation model for microblaze
Hello, My design is an spartan 3 with MicroBlaze. I'm running functional simulation in NCsim ( CADENCE ). Does anyone knows how to intergrate an rtl model of the microblaze in the functional simulation? I found some .vhd files but they are all encrypted. Xilinx did not givve me answer about that yet. Doe... 5 May 2010 18:14

Floating point unit in microblaze
Hi to all, I am the begginer in microblaze. I want to just print the value of the float variable "fpu" (=2.345) on the uart. can you please tell me how to write it in the microblaze (C), Can you tell me right from the include statements, because I not even know what are the header files it usesw to include floa... 6 May 2010 06:20

sopc builder custom component and passing parameters to VHDL package
I have written a custom SOPC builder component in VHDL. Right now I have SOPC builder auto-generating a package that contains custom type definitions that are used throughout my custom SOPC builder component. These type definitions are based on the settings input by the user in the SOPC builder GUI. This package... 7 May 2010 21:08

terasicblaster on CentOS 5.4 64 bit
Hi, I have problems getting my Terasicblaster working on a 64 bit Centos 5.4 machine, it reports "insufficient permission on some ports"! What does that mean and what can be done? /michael ... 5 May 2010 10:24

2010-04-30 new IAR FPGA EDA PCB circuit model or schematic programs added
2010-04-30 new IAR FPGA EDA PCB circuit model or schematic programs added forsalesoftware, for sale software, If you don't have enough money to buy needed software or think desired software isn't worth the price, then this service is right for you. We make software to be near you. Order any software you need for... 5 May 2010 04:56

Unecessary simulation paths
Hello, While using Qurtus II with a design that has only one section where timing is critical I got on the classical timing analyzer the relevant warnings about what it finds and that is absolutely fine and as expected. However on the remaining part of the design, (some quasi static configurations etc) tha... 6 May 2010 11:53

FIFO Depth Calculation
Hi All What could be the optimal buffer for an asynchronous FIFO with the Write clock at 50 MHz and the Read clock is 25 MHz Data is coming as 8 bits with each clock write . There is no idle cycle. We have to keep the synchronization latency also into account. Thanks Vips ... 6 May 2010 06:20

FIFO Depth Calculation
Hi Guys What could be the optimal buffer for an asynchronous FIFO with the source clock at 50 MHz and the Read clock is 25 MHz Data is clming as 8 bits with each clock write . There is no idle cycle. We have to keep the synchronization latancy also into account. Thanks Vips ... 4 May 2010 03:31

PCI Interrupt
Hi, I have some problems to let the FPGA generate an interrupt and to detect this interrupt on the computer (via PCI). Below you find a part of the VHDL-code from the PCI core generated by Xilinx Core Generator. Everytime data is written on the PCI bus the interrupt (INTR_N) will be asserted. Beneath that ... 4 May 2010 07:52

ISE 11.1 - readmemh issues
Hi guys, I'm porting my LatticeMico32 SoC across to a different FPGA board which uses a Xilinx Spartan3A (XC3S700A; the board is an Enterpoint Drigmorn2). I've got most of it moved across, but the Boot ROM is being difficult. This was implemented using the Altera ROM generator and a MIF file, but obviously i... 3 May 2010 22:01