FPGA
in [Hardware]
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antti alive message just to let all know I'm fine and not forgotten the brain release, not given up but the time til embedded is just crazy all things happening at worst time.. as usual :) and as usual, i'd be around the same stand as last year, if anyone drops by.. Antti ... 26 Feb 2010 01:58
Xilinx iodelay Intuitively, the iodelay found in Xilinx parts should be just a tapped delay line. But the need for a reference clock at a precise frequency indicates otherwise. Does anyone have any insight into how these are implemented? I'm not looking for an exact answer, but any reasonable explanation would be appreciated. ... 24 Feb 2010 18:50
timing constraint syntax/fpga editor info What is the syntax of this below constraint? I am using xilinx 11.4, spartan 6, and VHDL I have a signal say "a" that goes to 2 different "obufds". The delay between this "a" signal to the pins/pads are 4.8 ns and 2.8ns. Can I have a constraint that these 4,8 and 2,8 ns delays are smaller like 1 ns and close t... 24 Feb 2010 07:30
data2mem and rodata/data (Xilinx) I have just constructed a bootloader for a Xilinx FPGA. I am trying to get my main application converted to MCS using the flow described in XAPP482 (run data2mem and then xapp482.exe). The issue I'm having is that data2mem seems to ignore .rodata and .data sections in the .elf file, leaving me with uninitialized memo... 24 Feb 2010 13:06
FPGA platform?? Hi, I am a beginner at FPGA. I had a query that which platform is used for professional digital designs. Is it linux or windows?? --------------------------------------- Posted through http://www.FPGARelated.com ... 4 Mar 2010 14:37
Triming timing constraints from pin ... Hi all, I'm working on a Virtex5 xc5vlx50 and in my design I need to use some block ram. I generated the core with core generator, but when I implement the design I got this warning during mapping: WARNING:Pack:231 - trimming timing constraints from pin hit2/RAM1/BU2/ U0/blk_mem_generator/valid.cstr/ramloop[... 23 Feb 2010 10:07
Looking for Ultimate RISC/MISC that runs LINUX Website I realize what I'm looking for might not be out there anymore but I'm trying to give it my best shot. A couple of years ago I came across a website that somebody put up describing an ultimate RISC or MISC processor they were developing. One of their goals was to be able to run LINUX on it. Was having a conversat... 22 Feb 2010 19:47
Call for papers: EISWT-10, Orlando, USA, July 2010 It would be highly appreciated if you could share this announcement with your colleagues, students and individuals whose research is in enterprise information systems, information technology, e-commerce, web-based systems, data-mining and related areas. Call for papers: EISWT-10, Orlando, USA, July 2010 The 20... 21 Feb 2010 09:15
Call for papers: HPCS-10, Orlando, USA, July 2010 It would be highly appreciated if you could share this announcement with your colleagues, students and individuals whose research are in parallel computing, distributed systems, operating systems, computer architecture, grid-computing, VLSI, and related areas. Call for papers: HPCS-10, Orlando, USA, July 2010 ... 21 Feb 2010 09:15
State machines in Quartus I'm trying to get Quartus to recognize my state machines. I'm using version 9.0. I tried generating a state machine using the State Machine Wizard, but after compiling, if I try to look at it with the State Machine Viewer I get "This design has no State Machine." I tried to copy the Verilog code from the Help f... 21 Feb 2010 15:59 |