FPGA
in [Hardware]
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Virtex 5 GTP I have created a GTP wrapper for and have used the provided testbench to run a simulation. --------------------------------------- Posted through http://www.FPGARelated.com ... 21 Mar 2010 10:28
Finally, selling my old Xilinx/Viewlogic software package On Mar 21, 7:00 am, Peter <pe...(a)peter2000.co.uk> wrote: http://cgi.ebay.co.uk/ws/eBayISAPI.dll?ViewItem&item=290416326824 x----------x What? I have tons of those ;-)))))) ... 24 Mar 2010 18:07
Update init data in dualport BRAM without re-run anything? Hi all, There's an instance of BRAM in spartan3 device. I used coregen with *.coe file to init the data for the memory module My question, is there anyway to edit the mcs file (we use flatform flash for config) to change the content of init data ..."without spend 20 minutes to re-run the whole ISE processes ... 23 Mar 2010 12:26
wishbone Hi everyone, I'm just about to start an implementation of an open spacewire IP core (still trying to understand under which license, GPL, LGPL, CeCILL...) and I was wondering whether is a good idea to have a wishbone interface implemented. I am pretty new to SoC bus and even though google is "one of my best f... 25 Mar 2010 05:44
Spartan 3 Starter Kit Example Hi, I wrote a small example for the Digilent Spartan 3 Starter Kit. It uses the sram to store graphics data. Actually basing on this module I wanted to code a fractal generator. Here is the link, maybe someone finds it useful : http://tokis-edv-service.de/index.php/beispiele/spartan-3-example-1 The last test is a... 12 Apr 2010 15:52
Xilinx only on Avnet now Hi all, seems that Xilinx has decided to have only one distributor... and NuHorizons seems out of business. Does anybody know the reason behind? I believed was a good idea to have have the opportunity to buy from 2 distributors. ... 20 Mar 2010 17:43
Bus Master DMA with PCI Express Hi, I'm working with the xilinx xapp1052 Bus Master DMA model. The data received through DMA on the PCI-Express link is written to the fpga Block RAM. I have added my design to this, which reads data from this block ram and processes it. A Read DMA transfer is configured with a TLP size & TLP count and then t... 18 Mar 2010 10:28
Any Experiences with the GN4124 PCI Express - FPGA bridge? > Anyone had any experiences with the GN4124? Or alternatively, with the PEX8311 by PLX, which is the only other chip I've managed to find that performs a similair task? The ultimate project goal is going to be a PCIe card with an FPGA talking to a mini-ITX running Linux, and I'm likely going to be the one ... 19 Mar 2010 14:20
Digilent Nexys2 board I received my new Nexys2 board today and fired it up. I already had a Basys and Nexys board so I wanted to see what this one had to offer. It is nice. Its larger so that the leds actually line up with the switches and you have room to actually plug in a canned oscillator. You may not need it because they upgra... 25 Mar 2010 04:37
Last Call for Papers Reminder (extended): The World Congress on Engineering WCE 2010 CFP: The World Congress on Engineering WCE 2010 From: International Association of Engineers (IAENG) WCE 2010: London, U.K., 30 June - 2 July, 2010 http://www.iaeng.org/WCE2010 Draft Paper Submission Deadline (extended): 23 March, 2010 The WCE 2010 is organized by International Association of Engineers (IAENG... 17 Mar 2010 23:23 |