FPGA
in [Hardware]
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what is incorrect about my usage of array with port entity? library ieee; library work; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity delay_line_interleaved is generic( numtaps : integer := 18; wordlength_in : integer := 14; coefflen : integer := 20 ); port( -- INPUT PORTS -- clkin : in std_logic; rst : in std_logic; ... 17 Feb 2010 12:12
Data2Mem ? BlockRAM ? Init BMM and MEM Please help me I have really mess in my head with titles above. A have got custom processor that uses RAM which is created from Block RAMs. RAM is generated from CoreGen. I was initilizing BlockRAM's using .coe file. But it takes 'hours' to update code/data in .coe file and reimplement design. I wish to update d... 23 Feb 2010 15:50
EDK 11,1 on Windows 7, 32 Bit Hi my co-worker has a problem with EDK (used on w7, 32bit) OLD project can be built but any new projexcts created stop during implementation xilinx claims that the following table http://www.xilinx.com/ise/ossupport/index.htm is UPTODATE OS support list for Xilinx tools, in that table win7 is missing so... 22 Feb 2010 06:19
Differential Signaling Buffer Hi Has anyone made use of the Differential Signaling Buffer ipcore in EDK??? I have read the pdf accompanying the ipcore and managed to add it properly. But I am confused as how to connect the output of this buffer to a custom fifo i have created. please help!!!! -------------------------------... 17 Feb 2010 00:01
Differential Signaling Buffer Hi Has anyone made use of the Differential Signaling Buffer ipcore in EDK??? I have read the pdf accompanying the ipcore and managed to add it properly. But I am confused as how to connect the output of this buffer to a custom fifo i have created. please help!!!! ----------------------------------... 16 Feb 2010 00:25
The more you read, the more you are confused: about Intel's a patent Hi, Recently I read Intel's a patent "Apparatus and a method for embedding dynamic state machines in a static environment". http://www.google.com/patents?hl=en&lr=&vid=USPAT5712826&id=yqIeAAAAEBAJ&oi=fnd&dq=5712826&printsec=abstract#v=onepage&q=&f=false It direct uses the first level of latches in a normally 2 ... 17 Feb 2010 00:01
Intel's super-pipeline logic circuit paper is found Hi, We talked about Intel's super-pipeline logic a few weeks ago, using latch to replace flip-flops. Now I found the paper: patent number: 5796282. http://scholar.google.com/scholar?q=5796282&hl=en&btnG=Search&as_sdt=2001&as_sdtp=on Weng ... 15 Feb 2010 18:52
rocketio TX delay between sata0 and sata1 Hi, I'm workng with MGT as GT_CUSTOM. I use the MGT for transmiting to pulses of .66ns(1/15Ghg). I check all the delays with FPGA editor and all was ok, but I mesure the pulses at the SATA conector and there are a delay between SATA0 and SATA1 of 500ps. I simplified the program as much as posible and this delay is... 22 Feb 2010 22:01
Can the Altera USB cable attach to a KVM XP VM? I have a KVM XP VM running on Fedora 12. I'm trying to run SignalTap on the VM however I can't get the VM to see the USB cable. Virt-manager sees the cable and I've attached it to the VM but XP doesn't see it. Has anyone been able to attach an Altera cable to a KVM VM? p.s. the reason that I'm trying to do thi... 15 Feb 2010 12:02
instructor solution manual for An Introduction to Ordinary Differential Equations (James C. Robinson) Hello, Do you have Dynamics of Flight - Stability & Control 3e - Solutions Manual? --- frmsrcurl: http://compgroups.net/comp.arch.fpga/instructor-solution-manual-for-An-Introduction-to-Ordinary-Differential-Equations ... 14 Feb 2010 11:45 |