FPGA

Quartus II IDE freezing on Arch 64
Hello, all. I just got quartus II linux web edition operational on my Arch64 lappy. This involved installing a bunch of libraries, tweaking my /etc/ issue file to correct something that altera was getting upset about, and LD_PRELOADing a library or two. All a lot of messing around, but it ended up actually working... 22 Feb 2010 10:42

Question about altera root-port for Stratix4GX Hard IP
I have a question about Altera Stratix4GX PCIe Hard IP root port question. As per my understanding, the back end of the root-port supports Avalon ST Bus thorugh which I can feed TLPs to pass transactions downstream using the Hard IP root port. Is it possible to put it in a mode where all the transactions are pass... 20 Feb 2010 22:25

Legal syntax for VHDL expression
I am writing a case statement and it doesn't seem to like an attribute as a selection expression. Is an attribute not a legal item in an expression? It flags an error at the "of" on the first line saying 'keyword "is" expected' and at the beginning of the last line shown here saying 'keyword "end" expected' ... 20 Feb 2010 21:18

how to read bmp file in vhdl
helo i am in B.E.-E&TC,doing project on DIGITAL WATER MARKING TECH.. I need to convert matlab code in to vhdl for downloading,if not then how to read bmp file in vhdl?..Can u please help me out.. ... 22 Feb 2010 07:24

System design in FPGA
Hi all, I am a budding FPGA designer and I am in the process of designing first system. Until now I have partitioned my system into various entities, each entity implementing a small part of the system. It is also easier for implementation. However I have found myself in routing a lot of signals from one entity ... 23 Feb 2010 09:00

Call for Papers: The 2010 International Conference on Wireless Networks (ICWN'10), USA, July 2010
It would be most appreciated if this announcement could be shared with individuals whose research interests include wireless networking, communication systems (including telecommunications) and pervasive systems. Thank you. ------- CALL FOR PAPERS ICWN'10 ... 19 Feb 2010 01:06

BRAM16 error
Hi all, I have a Spartan 3 Starter Board. I want to make a simple application with microblaze. But when I generate the bitstream an error error has appeared wich is: ERROR:Pack:2310 - Too many comps of type "RAMB16" found to fit this device. ERROR:Map:115 - The design is too large to fit the device. Please chec... 21 Feb 2010 08:09

Derived clock violation in Virtex4
Hi, I have a V4 with input clock frequency running at 130MHz. This clock goes into a DCM then CLK0 goes out to other logic. The CLK0 net is named as "derived_clock" by Synplify. Now the timing report on the input 130MHz is fine (positive slack) but the derived_clock doesn't meet timing. How to contrain that? ... 23 Feb 2010 17:00

Unpredictable design
Hello ! I have a very big problem. I created a simple procesor and on simulation it works fine, on step mode it works fine but when it is running on full speed of clock it got crazy... :( It should execute instruction i order 0.1.2.3.4.5 (Program Counter values and PC is connected to leds) and it executes sometimes ... 20 Feb 2010 21:18

How a state machine is constructed using latches?
Hi, Sometimes, when an if statement misses a "else" statement part in a two-process method for a state machine, a latch-type state machine would be built. I always wondering how the state machine is built: using all latches for the state machine or using only one latch for the state which misses a "else" statem... 25 Feb 2010 20:29