FPGA

Draft paper submission deadline is extended: HPCS-10, Orlando, USA
It would be highly appreciated if you could share this announcement with your colleagues, students and individuals whose research are in parallel computing, distributed systems, operating systems, computer architecture, grid-computing, VLSI, and related areas. Draft paper submission deadline is extended: HPCS-10... 13 Feb 2010 19:24

VHDL vs Verilog (quote found)
John_H wrote: The quote predates Oct 200 as noted by the post: http://www.fpga-faq.com/archives/26475.html#26480 i think that you missed one zero :-) But I'm surprised that the title of this post is exactly the same as mine. Damnit, I want to be original and I write the same stuff as others again :-/ ... 13 Feb 2010 09:16

VHDL vs Verilog
hi, recently I read a quote about VHDL vs Verilog, along the lines of "VHDL is made by SW people who don't understand HW and vice versa"... Does anybody know the exact wording and origin ? yg -- http://ygdes.com / http://yasep.org ... 15 Feb 2010 13:10

Why is following Verilog code snipper considered a Latch
I am not sure why the QuartusII synthesis tool is considering ReqInFifoDataIn[72] a latch and not a flip-flop? ReqInFifoData[72] is clearly defined as part of synchronous always block. It is getting used by wTag signal - Here I am anding the D input of the Flip-Flop and Qn output of the same D flip-flop. The pur... 12 Feb 2010 20:12

Test Post
I posted a query about 10 layer PCBs for a new board I'm doing. I caught a reply by Rickman at home via Google, but it seems to have disappeared now. My usenet connection's normally pretty reliable so I'm not sure what's going on. Will this get out? Nial. ... 12 Feb 2010 12:17

QDRII on StratixIII pinout strangeness
Using QDRII x18 in 2-burst mode, I assume that the data/adr/cmd bus are all DDR signals using the same clock domain (except the read and write signal wich are single data rate) The docs say there are limitations on where to put the data bus, and then I can put the adr/cmd on what is left in the bank. This app... 12 Feb 2010 05:27

What is the basis on flip-flops replaced by a latch
Hi, I finally understand the reason when a flip-flops can be replaced by a latch. Here is the excerpt from the paper "Atom Processor Core Made FPGA Synthesizable" Optimized for a frequency range from 800MHz to 1.86Ghz, the original Atom design makes extensive use of latches to support time borrowing along the ... 18 Feb 2010 20:42

Multple architectures in ISE top level module?
ISE drives me crazy! One of the most powerful features of VHDL is the ability to handle multiple architectures and configurations for the same entity. This makes for efficient simulation, regression testing, and promotes code reuse. I've spent way too many hours trying to figure out problems with ISE s... 11 Feb 2010 12:46

Actel FPGA corePWM IP
Hi, I wish to know if anyone of you out there is using an Actel FPGA board and knows how to generate PWM signal using the corePWM IP? If you do, please let me know as i am having a hard time trying to follow the application note provided by actel on the corePWM. Thank you! ... 12 Feb 2010 08:54

Call for Paper The International Journal of Computer Science (IJCS)
Call for Paper The International Journal of Computer Science (IJCS) publishes original papers on all subjects relevant to computer science, communication network, and information systems. The highest priority will be given to those contributions concerned with a discussion of the background of a practical problem,... 11 Feb 2010 00:39