FPGA

What MAXIM chip is used on Spartan 3E 1600E Microblaze Board for ??RS232 communication?
Alex <victous(a)gmail.com> wrote: On 2 ???, 09:14, glen herrmannsfeldt <g...(a)ugcs.caltech.edu> wrote: Alex <vict...(a)gmail.com> wrote: I have started using Xilinx Spartan3E 1600E Microblaze Development Board and want to use its RS232 facility in my project. This board has two RS232 connectors but ... 2 Feb 2010 14:36

What MAXIM chip is used on Spartan 3E 1600E Microblaze Board for ?RS232 communication?
Alex <victous(a)gmail.com> wrote: I have started using Xilinx Spartan3E 1600E Microblaze Development Board and want to use its RS232 facility in my project. This board has two RS232 connectors but I cannot figure out what UART it uses. I was searching for UART chip on the board (I was actually searching fo... 2 Feb 2010 21:55

What MAXIM chip is used on Spartan 3E 1600E Microblaze Board for RS232 communication?
Hello All, I have started using Xilinx Spartan3E 1600E Microblaze Development Board and want to use its RS232 facility in my project. This board has two RS232 connectors but I cannot figure out what UART it uses. I was searching for UART chip on the board (I was actually searching for a MAXIM chip) and have seen... 2 Feb 2010 14:36

Single Port Rom created by Core Generator configurable by generic values!!!!
>On 1 =C5=9Eubat, 16:45, Enes Erdin <eneser...(a)gmail.com> wrote: On 1 =C5=9Eubat, 14:33, "bellatoise" <arianapo...(a)gmail.com> wrote: Hi, My query is the next: I'm working with Xilinx Ise Design Suite 11.1. I need some ROMS with differents values of depth, width and initializ... 2 Feb 2010 14:36

How can I convert size requirements from Altera devices to Xilinx devices?
I have two designs for an Altera chip that use approximately 6,000 and 24,000 logic elements. I am looking at moving to Xilinx tools, but am not sure how these numbers translate across manufacturers. I have seen Xilinx FPGA with gate counts cited, but I am not sure what those number mean. Can anyone provide some... 2 Feb 2010 14:36

Single Port Rom created by Core Generator configurable by generic values!!!!
Hi, My query is the next: I'm working with Xilinx Ise Design Suite 11.1. I need some ROMS with differents values of depth, width and initialization files that I want to instantiate in one proyect. I need a generic ROM, so I created one with Core Generator and I got its HDL code using View HDL functional Model. T... 2 Feb 2010 14:36

Connecting ADC chip to sparta 3 a dsp
hi there I have an ADC chip which is working in the LVDS mode. The data out(D0+,D0-,......D13+ and D13-),along with data clock out(DC0+,DC0-) and out of range(OUR) are connected physically to Sparta 3a dsp. My question is how do I directly collect these LVDS signals in my sparta 3a dsp core. How do I g... 2 Feb 2010 14:36

Constraining minimum hold times (Xilinx)
Hello, is there a way to constrain minimum hold time requirements with ISE? I am trying to write to an FT2232H in synchronous FIFO mode. The FT2232H supplies a 60 MHz clock and specifies 11 ns setup and 0 ns hold. As the FT2232H supplied clock can stop, using a DCM to retime the clock will at least require the... 6 Feb 2010 14:05

Quartus Web Edition on Linux - no simulation?
I just installed Quartus II Web Edition 9.1 on linux. I compiled a simple test project and only then I noticed that simulation is unsupported! It's supported on the Windows version, so how come this discrepancy? Are we supposed to dump each and every edit onto the board and debug on the board? They might as well no... 2 Feb 2010 14:36

synthesizing a completely empty design for an FPGA to measure ?quiescent current
EE EE <eengr.usa(a)gmail.com> wrote: I want to synthesize a completely empty design, no clocks no combo and no sequential logic for a xilinx FPGA using ISE. In the old days there was LCAEdit that would allow one to edit the design at the LUT/switch level. I think if you open LTAEdit you can just say SAVE w... 2 Feb 2010 14:35