FPGA
in [Hardware]
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To get higher clock frequencies at output using propagationdelays. On Tue, 09 Feb 2010 20:11:02 -0600 "Pallavi" <pallavi_mp(a)n_o_s_p_a_m.rediffmail.com> wrote: Hi, I'm implementing this project where I've to generate higher output clk frequencies using DCM module. I have used a counter for delay generator, for propagation delays(Pls suggest if there is any other m... 10 Feb 2010 12:13
Reading UDP with FPGA Hi all, as the title says I have to read some information stored in UDP packet with an FPGA. Now I'm evaluating 3 options: 1) Use an external processor and send data to FPGA through dedicated lines 2) Use a microcontroller embedded into the FPGA (i.e. microblaze, since I'm working on a Xilinx) 3) Write an ha... 23 Feb 2010 02:26
To get higher clock frequencies at output using propagation delays. Hi, I'm implementing this project where I've to generate higher output clk frequencies using DCM module. I have used a counter for delay generator, for propagation delays(Pls suggest if there is any other method). I have also instantiated the DCM module with an input freq of 50MHz and an output frequency of 320 MHz.... 15 Feb 2010 16:35
Running BMD design on a 64 bit machine Hi, i have implemented a BMD design using xapp1052. it is running successfully on a 32 bit machine. but when i run it on a 64 bit machine i am facing a problem the problem is that when i set the register DCSR0 bit 1 and try to read it a blue screen appears with the message "HARDWARE FAILURE" . but on the 32 ... 9 Feb 2010 09:26
Xilinx ISE 11.1 crash - Visual Studio error Could some Xilinx ISE guru provide some hints for my problem ? I am trying to synthesize a simple 4K RAM block with Xilinx ISE. About half- way through execution, I get an error message, inside a Visual Studio dialog box, stating that xst.exe ( the Xilinx synthesis executable) has encountered a problem and would I ... 9 Feb 2010 12:48
using an FPGA to emulate a vintage computer Has anyone created a copy machine of an old system using an FPGA? I was wondering if it would be possible to take an entire SWTPC 6800 and compile the schematics and have it run on an FPGA board.? Wouldn't even have to be the latest Xylinx product, I suspect. ... 10 Mar 2010 15:18
ISPLever, devlist command Hello, i use ISPLever 7.1 - 8.0, but I have a major trouble : When I try to launch devlist -l command in the ISPLever console, the result is empty. BUT this command should return the list of all the devices supported by the tool. Do someone know this issue? Do somenone know how to fix it ? Thanks. ... 5 Feb 2010 11:38
Simulating Spartan 3A pins in ltspice Xilinx claims: We recommend the use of IBIS models whenever possible. IBIS models for many devices are often available as free downloads. Using IBIS provides the following: * Faster simulation speed. * Elimination of non-convergence. * Strong support from virtually all EDA vendors. Well, when I... 8 Feb 2010 01:16
Quartus II - Generating Verilog from MegaWizard plugins I'm using the MegaWizard plugin manager on Quartus II 9.1 on linux and I can't get it to generate any Verilog files for me. It does generate VHDL files. There is an option to generate Verilog but it generates VHDL as far as I can see. ... 4 Feb 2010 16:48
DONE_cycle:6 setting neccessary in bitgen Hi *, I recently designed a board with a Virtex 5 on it, which I got back from the assembly line a few days ago. This is not the first board I've designed, and I've used many FPGA-boards from others before, but I've never come across this problem: FPGA configuration via JTAG will only work if the bitfile is ge... 11 Feb 2010 22:57 |