FPGA
in [Hardware]
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Compiling a design in Quartus that doesn't fit I want to be able to generate an encrypted netlist of a core using Quartus. Does Quartus have a switch that allows you to compile a design that doesn't fit into an FPGA? The issue is that the ports on the core exceed the number of pins on any device. ... 11 Mar 2010 12:15
Xilinx ISE Webpack Schematics Hi ASICFriends, I'm using XILINX ISE WebPack, release 8.2 (due to compatibility issues with older projects). Does anyone know how to make some symbol inputs to be "don't care" inside an ISE schematic ? For example, at some mux inputs ? As we can do on VHDL or Verilog ? I expect that such issues would allow the ... 12 Mar 2010 12:45
CFP with Extended Deadline of Mar. 21, 2010: The 2010 International Conference on Grid Computing and Applications (GCA'10), USA, July 2010 It would be greatly appreciated if this announcement could be shared with individuals whose research interests include grid computing (including cloud and parallel and distributed processing). Thanks. ------- CALL FOR PAPERS Paper Submission Deadline (EXTENDED): March 21, 2010 ... 10 Mar 2010 14:10
Tier Logic introduces the world's first 3D FPGA The world's first 3D FPGA has arrived! We have a very compelling and cost effective solution. Come check it out folks. www.tierlogic.com Jeff ... 15 Mar 2010 15:47
Translate Error: ngd build 604 Hi, I'm doing this project using ISE 9.2i and am getting the ngd build error: 604 during translation. Can anyone please let me know how to resolve this error. I'm able to synthesize the code successfully. Thanks. --------------------------------------- Posted through http://www.FPGARelated.com ... 12 Mar 2010 20:38
Spartan3AN DDR2 - bad writing zeros I've got a problem with my DDR2 (MT47H32M16) on my Spartan3AN board. I use MIG 2.3 controler. The burst lenght is 4. When I'm writing the data like x"A1A1B2B2" or x"01010101" everything works. I'm reading the data after data_valid is set and writing to internal registers. Then I'm sending it to RS232. Problem is... 11 Mar 2010 05:37
Call for Papers Reminder (extended): The World Congress on Engineering WCE 2010 CFP: The World Congress on Engineering WCE 2010 From: International Association of Engineers (IAENG) WCE 2010: London, U.K., 30 June - 2 July, 2010 http://www.iaeng.org/WCE2010 Draft Paper Submission Deadline (extended): 18 March, 2010 The WCE 2010 is organized by International Association of Engineers (IAENG... 9 Mar 2010 01:18
Why doesn't this situation generate a latch? Hi, I have a question about when to generate a latch. In Example_1 and Exmaple_2, I don't think it will generate a latch. I don't know why. Example_1: process(RESET, CLK) Begin If RESET = 1 then StateA <= S0; Elsif CLKevent = 1 and CLK = 1 then If SINI = 1 then StateA <= S0; Elsif E2 ... 22 Mar 2010 15:28
Some Active-HDL questions I have an evaluation copy of Active-HDL, and am having some (presumably) newbie issues with it. I went through their VHDL tutorial, but it has all sorts of visual editors in the flow that I'm not interested in. I tried importing my Modelsim XE project, and that sort of worked, but it didn't convert my "do" file.... 11 Mar 2010 06:42
Call for papers: HPCS-10, USA, July 2010 It would be highly appreciated if you could share this announcement with your colleagues, students and individuals whose research are in parallel computing, distributed systems, operating systems, computer architecture, grid-computing, VLSI, and related areas. Call for papers: HPCS-10, USA, July 2010 The 2010... 7 Mar 2010 08:29 |