FPGA

Virtex-5 FPGA PCIe card
I am working with a Virtex-5 FPGA PCIe-based board and want to create three interfaces (lanes?). One that is a two way serial interface running at 1 MHz. Another running at 1 MHz but only input to the board. The last interface or lane will be 16 bit input only running at 28 MHz. I am reviewing the Avnet Develop... 20 Apr 2010 15:41

How to find latches in Xilinx ISE 10.1
Greetings, The synthesis report on my design tells me that I have caused 3 latches to be created: 1 LDC and 2 LDP. I didn't intend to create any... Rather frustratingly, the reports aren't telling me which signals are associated with these latches, so that I can fix my code! My colleagues can't remember what the ... 13 Apr 2010 10:33

MPEG Reading material
Can anyone recommend a cross beween reading material and reference material for MPEG coding? I am familiar with JPEG, and the JFIF file structure and would like to know more about MPEG, preferably to include MPEG-4 with a view to coding MPEG4 streams. ... 20 Apr 2010 15:41

Microblaze Reset
Is it possible to define an internal reset for a microblaze system. Idealy I would like it to come from the DCM locked signal. Do I need to define it in the XBD file or is that just for external ports? Thanks Jon --------------------------------------- Posted through http://www.FPGARelated.com ... 13 Apr 2010 13:55

Declaring gated clocks
Hi, I am working on moving an ASIC design to FPGA. For this i am using synplify pro synthesis tool. But, the tool does not seem to recognise all the gated clocks [sometimes because it cant recognise the base clock]. is there any alternative method to declare the base clock for the gated design other than usin... 10 Apr 2010 14:35

Module wise FPGA resource utilization report
Hello, We are trying to determine the number of slices that a specific module in the design consumes upon synthesis. Is there a way to generate a report that shows resource utilization per module using Xilinx ISE Webpack v11.5 ? Thanks and Regards, Vikram. --------------------------------------- P... 14 Apr 2010 07:39

Problems with data2mem
Hello everybody, long time no see. ;-) Now that I return to FPGA design at least for hobby purposes, I have some trouble with data2mem. Iam using Webpack 11.1. I want to use Picoblaze in a Spartan 3A 700. For updating of the program memory I use data2mem, but without success. :-( Here is my bmm file ADDR... 9 Apr 2010 14:29

ISE Timing Constraints
I seem to be stuck on this one. I have 2 DCMS creating a 100MHz clock and a 125MHz clock derived from a common 25MHz clock. Signals cross clock domains using grey-code and suitable multiple latches where appropriate. I am aware of metastable states etc and their consequences.. However when I specify a 4... 11 Apr 2010 05:48

I'd rather switch than fight!
I think I have about had it with VHDL. I've been using the numeric_std library and eventually learned how to get around the issues created by strong typing although it can be very arcane at times. I have read about a few suggestions people are making to help with some aspects of the language, like a selection ope... 20 May 2010 18:17

Spartan-3 dsp FG676 Vccint decoupling caps
Our PCB guy saying there's no enough room for Vccint pins (all converge at center of the chip) so that each pin has one 0.01 uF decoupling cap. As a result we have just 12 caps for 23 vccint pins !!! Wonder if anyone out there has similar pcb placement problem like us, and how you solve it ? TIA ... 9 Apr 2010 12:14