FPGA
in [Hardware]
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How to convert Verilog in to VHDL code I have tried to convert the following verilog code manually in to VHDL in order to use it in my project which is written in vhdl. But I am not able to get the same RTL results. Would you help me in converting the next module or tell me how to instantiate vhdl into verilog please? thanks in advance =======... 5 Apr 2010 10:28
Is there a way...(Thanks all) On 4/4/2010 12:33 AM, PureSine wrote: Thanks all very much for elegant solutions. I surely remember all of them for different applications but for current application I guess simplest solution is to just alter DDS code and implement division inside it as Symon said. I just need to subtract subtraction(division)... 4 Apr 2010 03:56
Is there a way to implement division by variables other than 2 in ?single clock with XST ? John_H <newsgroup(a)johnhandwork.com> wrote: (snip) Great advice. You can also perform several stages of the division per clock cycle reducing a 16-bit division to 4 clock cycles, for instance. There are better ways to perform pipelined division but you'll need to consider this approach regardless. I... 3 Apr 2010 18:07
Is there a way to implement division by variables other than 2 in single clock with XST ? PureSine <Green.Tech.Coder(a)gmail.com> wrote: Hello, I need to do some DSP operations preferably with Spartan 3. I need to divide output of a fast DDS by a variable but XST says it can only implement a divider with constants of power of 2. One way would be to recursively subtract divisor from dividend bu... 4 Apr 2010 08:14
Which is the most beautiful and memorable hardware structure in a ?CPU? In comp.arch.fpga MitchAlsup <MitchAlsup(a)aol.com> wrote: (snip) It was not so much that I was concentratng on Linpack, We (shebanow and I) were trying to build a machine that could perform as if it were a vector machine on vectorizable codes (without vector instructions:: i.e. native 88100 instructions ... 5 Apr 2010 14:57
Is there a way to implement division by variables other than 2 insingle clock with XST ? Hello, I need to do some DSP operations preferably with Spartan 3. I need to divide output of a fast DDS by a variable but XST says it can only implement a divider with constants of power of 2. One way would be to recursively subtract divisor from dividend but that needs many cycles which is not suitable for me.... 3 Apr 2010 17:01
ISE block RAM inference I'm doing a design in a XC3S250E, using ISE 10.1.03. For some reason my generic dual-port RAM (with synchronous read) seems to be inferred as distributed. I'm fairly sure that a slightly earlier version of the design worked OK, but I don't know what has changed. I have "RAM extraction" checked, and "RAM Style" ... 2 Apr 2010 20:22
Microblaze and DDR2 Is it possible to interface DDR2 memory to a Microblaze processor by not using the MPMC. I have my own DDR controller that I want to use. Cheers Jon --------------------------------------- Posted through http://www.FPGARelated.com ... 17 Apr 2010 14:05
Raggedstone2 - PCIe Spartan-6 Board - Pre-release information Prerelease information on our Spartan-6 based Raggedstone2 PCI Express board is available http://www.enterpoint.co.uk/raggedstone/raggedstone2.html. For those of going to ESC in San Jose later this month this board will be showing, along with our extensive range of other boards, at our stand there. We have maint... 2 Apr 2010 04:56
Xilinx XPS crash on Linux ISE10.1 ISE11.х "libfontconfig" mast be compile with "libexpat" (as in RH, Centos and so on), but not with "libxml2". take|compile libfontconfig with libexpat (take from CentOS) and copy in ~/lib. In ISE/settings64.sh(settings32.sh) rewrite LD_LIBRARY_PATH=${XILINX}/lib/${PLATFORM}:${LD_LIBRARY_PATH} with LD_LIBRARY_PA... 2 Apr 2010 04:56 |