FPGA
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Can Spartan-6 Support M-LVDS ? Does the Spartan-6 LX family or Spartan3A support the Multipoint-LVDS specifications? We need input and ouput buffers compliant to M-LVDS type1 and types 2. Also , the buffers should be 5V LVTTL tolerant. ... 9 Apr 2010 13:22
Debug multiple FPGAs using ChipScope via single JTAG chain Dear All, We are planning to design a board with four FPGAs to emulate X86 CPU. The FPGAs JTAG ports are serially chained together. My problem is that whether the Xilinxs ChipScope can support debugging multiple FPGAs via a single JTAG chain at the same time? So we can set different trigger conditions to diffe... 12 Apr 2010 05:53
Cannot download ELF; I-Side Memory Access Check Failed Hello, I'm a graduate student and I have a project on the ML402 (Virtex-4) board under EDK 11.2, and I am unable to download a specific ELF I have created to the board. Other software applications (both EDK generated and programmed by myself) can be successfully downloaded and run as part of this EDK project, bu... 8 Apr 2010 18:33
Summing with carry problems ... Hi, again me ... :-) ... I have one problem with SUM of 3 signal. ############# [CODE]############# signal E : std_logic_vector (3 downto 0); signal Z : std_logic_vector (3 downto 0); signal r : std_logic; signal total : std_logic_vector(4 downto 0); total <= Zi + Ei + r; ############# [/CODE]#######... 8 Apr 2010 20:48
EDK map error 1492 - incompatible programming error >On Dec 23, 11:15 am, Gabor <ga...(a)alacron.com> wrote: On Dec 23, 1:50 am, "Andrew W. Hill" <aquaregi...(a)gmail.com> wrote: I'm using EDK 10.1, specced for the ML501. When I reach the mapping phase, I get the following error (several times): ERROR:PhysDesignRules:1492 - Incompatible programmin... 7 Apr 2010 22:30
VHDL coding HI, I want to use sll operator(shift operator)specified in VHDL93. I am using xilinx ISE simulator.The compilation of code fails giving error HDLParsers:808- sll can not have such operands in this context. I think that i should activate VHDL93 in the simulator.MODELSIM has the facility to activate it through compi... 8 Apr 2010 06:08
Case with HEX value ... Hi, I have write simple lockup table: #################### [CODE] #################### din : in std_logic_vector (3 downto 0); dout : out std_logic_vector (1 downto 0) begin process(din) begin case(din) is when "000" => dout <= conv_std_logic_vector(2, 2); ... 8 Apr 2010 05:03
Extract single bit from std_logic_vector ... Hi, I have one problem to extract single bit from std_logic_vector, with use of HEX suffix. Ex: signal out : std_logic; signal in : std_logic_vector(7 downto 0); out <= in(x"03"); I use HEX for compatibility with C source ... When I check syntax with ISE I obtain an error, why ? Thanks. secure... 6 Apr 2010 06:22
A few LatticeMico32 questions Hi, It would seem the Lattice Mico32 support forum has gone dead (no posts/ replies since early February), so I'm asking this here in the hope there's an lm32 guru somewhere out there... I've (successfully) ported the LatticeMico32 CPU core to the Altera Cyclone II (terASIC DE1 platform, aka Cyclone II FPGA St... 14 Apr 2010 12:06
Multi-function pins in Spartan-6 Hi, I have a question about the multi-function pins in Spartan-6 FPGA (XC6SLX9). I would like to know if I can use the D0-D15 and A0-A25 config pins as general purpose IO pins because I am using a serial PROM to program the FPGA and so will not use BPI mode. I have read about the pins and I just want to be sur... 5 Apr 2010 14:57 |